8d82eb29d9b9c5ff513ef66d7d799de826dc3f4d
Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be set to values beyond their saturation point if loaded through non-increment/decrement mechanism. #114
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
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