bslathi19/PeakRDL-regblock
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Add precedence test. fixup docs

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Alex Mykyta
2022-02-28 22:05:24 -08:00
parent 404e7e8365
commit 9295cbb7c0
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README.md
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[![build](https://github.com/SystemRDL/PeakRDL-regblock/workflows/build/badge.svg)](https://github.com/SystemRDL/PeakRDL-regblock/actions?query=workflow%3Abuild+branch%3Amain)
[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)
# IMPORTANT
This project has no official releases yet and is still under active development!
# PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.