bslathi19/PeakRDL-regblock
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Alex Mykyta 9295cbb7c0 Add precedence test. fixup docs
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README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
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Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%