Add precedence test. fixup docs

docs/dev_notes/Validation Needed

@@ -142,10 +142,29 @@ X Warn/error on any signal with cpuif_reset set, that is not in the top-level
     addrmap. At the very least, warn that it will be ignored
 
 
-! "bridge" addrmap not supported
+X "bridge" addrmap not supported
     export shall refuse to process an addrmap marked as a "bridge"
     Only need to check top-level. Compiler will enforce that child nodes arent bridges
 
+X regwidth/accesswidth is sane
+    X accesswidth == regwidth
+        Enforce this for now. Dont feel like supporting fancy modes yet
+        X regwidth < accesswidth
+            This is illegal and is enforced by the compiler.
+        X regwidth > accesswidth
+            Need to extend address decode strobes to have multiple bits
+            this is where looking at endianness matters to determine field placement
+            Dont feel like supporting this yet
+    X constant regwidth?
+        For now, probably limit to only allow the same regwidth everywhere?
+
+
+X Do not allow unaligned addresses
+    All offsets & strides shall be a multiple of the regwidth used
+
+    X each reg needs to be aligned to its width
+    X each regfile/addrmap/stride shall be aligned to the largest regwidth it encloses
+
 ! async data signals
     Only supporting async signals if they are exclusively used in resets.
     Anything else declared as "async" shall emit a warning that it is ignored
@@ -154,27 +173,6 @@ X Warn/error on any signal with cpuif_reset set, that is not in the top-level
 ! Error if a property references a non-signal component, or property reference from
     outside the export hierarchy
 
-! regwidth/accesswidth is sane
-    ! accesswidth == regwidth
-        Enforce this for now. Dont feel like supporting fancy modes yet
-        X regwidth < accesswidth
-            This is illegal and is enforced by the compiler.
-        ! regwidth > accesswidth
-            Need to extend address decode strobes to have multiple bits
-            this is where looking at endinaness matters to determine field placement
-            Dont feel like supporting this yet
-    ! constant regwidth?
-        For now, probably limit to only allow the same regwidth everywhere?
-
-
-! Do not allow unaligned addresses
-    All offsets & strides shall be a multiple of the regwidth used
-
-    - each reg needs to be aligned to its width
-    - each regfile/addrmap/stride shall be aligned to the largest regwidth it encloses
-        --> Should i promote this check to the compiler? At least as a warnable condition
-            Currently i think I only do the more stringent case of block alignment.
-
 ! Add warning for sticky race condition
     stickybit and other similar situations generally should use hw precedence.
     Emit a warning as appropriate

docs/hwif.rst

@@ -48,4 +48,4 @@ For example, a simple design such as:
     hwif_in.my_reg[1].my_field.we
 
 For brevity in this documentation, hwif features will be described using shorthand
-notation that omits the hierarchcal path: ``hwif_out..<feature>``
+notation that omits the hierarchical path: ``hwif_out..<feature>``

docs/index.rst

@@ -2,7 +2,7 @@ Introduction
 ============
 
 PeakRDL-regblock is a free and open-source control & status register (CSR) compiler.
-This code generator that will translate your SystemRDL register descripton into
+This code generator that will translate your SystemRDL register description into
 a synthesizable SystemVerilog RTL module that can be easily instantiated into
 your hardware design.
 
@@ -16,16 +16,11 @@ your hardware design.
 Installing
 ----------
 
-.. important::
-
-   This project has no official releases yet and is still under active development!
-
 Install from `PyPi`_ using pip
 
 .. code-block:: bash
 
-   # NOT RELEASED YET
-   # python3 -m pip install peakrdl-regblock
+   python3 -m pip install peakrdl-regblock
 
 .. _PyPi: https://pypi.org/project/peakrdl-regblock
 

docs/limitations.rst

@@ -29,3 +29,15 @@ No partial writes
 
 Some protocols describe byte-level write strobes. These are not supported yet.
 All write transfers must access the entire register width.
+
+
+Register width, Access width and CPUIF bus width
+------------------------------------------------
+To keep the initial architecture simpler, currently ``regwidth``, ``accesswidth``
+and the resulting CPU bus width has some limitations:
+
+* All registers shall have ``regwidth`` == ``accesswidth``
+* ``regwidth`` shall be the same across all registers within the block being exported.
+* The CPU interface's bus width is statically determined by the ``regwidth`` used.
+
+I have plans to remove these restrictions and allow for more flexibility in the future.

docs/props/field.rst

@@ -533,7 +533,7 @@ paritycheck
 
 precedence
 ^^^^^^^^^^
-|EX|
+|OK|
 
 reset
 ^^^^^

docs/props/signal.rst

@@ -7,19 +7,19 @@ Signal Properties
 
 activehigh/activelow
 --------------------
-|EX|
+|OK|
 
 sync/async
 ----------
-|EX|
+|OK|
 
 Only supported for signals used as resets to infer edge-sensitive reset.
 Ignored in all other contexts.
 
 cpuif_reset
 -----------
-|EX|
+|OK|
 
 field_reset
 -----------
-|EX|
+|OK|