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Add precedence test. fixup docs

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Alex Mykyta
2022-02-28 22:05:24 -08:00
parent 404e7e8365
commit 9295cbb7c0
14 changed files with 164 additions and 55 deletions
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docs/limitations.rst
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@@ -29,3 +29,15 @@ No partial writes
Some protocols describe byte-level write strobes. These are not supported yet.
All write transfers must access the entire register width.
Register width, Access width and CPUIF bus width
------------------------------------------------
To keep the initial architecture simpler, currently ``regwidth``, ``accesswidth``
and the resulting CPU bus width has some limitations:
* All registers shall have ``regwidth`` == ``accesswidth``
* ``regwidth`` shall be the same across all registers within the block being exported.
* The CPU interface's bus width is statically determined by the ``regwidth`` used.
I have plans to remove these restrictions and allow for more flexibility in the future.