Add precedence test. fixup docs

test/README.md

@@ -6,10 +6,16 @@
 Testcases require an installation of the Questa simulator, and for `vlog` & `vsim`
 commands to be visible via the PATH environment variable.
 
-*Questa - Intel FPGA Starter Edition* can be downloaded for free from
-https://fpgasoftware.intel.com/ and is sufficient to run unit tests. You will need
-to generate a free license file to unlock the software: https://licensing.intel.com/psg/s/sales-signup-evaluationlicenses
-
+*Questa - Intel FPGA Starter Edition* can be downloaded for free from Intel:
+* Go to https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html?edition=pro&s=Newest
+* Select latest version of *Intel Quartus Prime Pro*
+* Go to the *Individual Files* tab.
+* Download Questa files. (Don't forget part 2!)
+* Install
+* Go to https://licensing.intel.com/psg/s/sales-signup-evaluationlicenses
+* Generate a free *Starter Edition* license file for Questa
+    * Easiest to use a *fixed* license using your NIC ID (MAC address of your network card via `ifconfig`)
+* Download the license file and point the `LM_LICENSE_FILE` environment variable to the folder which contains it.
 
 
 ## Vivado (optional)

test/test_precedence/regblock.rdl

@@ -0,0 +1,26 @@
+addrmap top {
+    reg {
+        field {
+            sw=rw;
+            hw=w; we;
+            precedence=sw;
+        } f_sw = 0;
+        field {
+            sw=rw;
+            hw=w; we;
+            precedence=hw;
+        } f_hw = 0;
+    } r1 @ 0x0;
+
+    reg {
+        default counter;
+        default sw=r;
+        default hw=na;
+
+        field {} f_sw_count[3:0] = 0;
+        field {} f_hw_count[7:4] = 0;
+    } r1_events @ 0x4;
+
+    r1_events.f_sw_count->incr = r1.f_sw;
+    r1_events.f_hw_count->incr = r1.f_hw;
+};

test/test_precedence/tb_template.sv

@@ -0,0 +1,26 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // Always write both fields from hardware
+    cb.hwif_in.r1.f_sw.next <= '0;
+    cb.hwif_in.r1.f_sw.we <= '1;
+    cb.hwif_in.r1.f_hw.next <= '0;
+    cb.hwif_in.r1.f_hw.we <= '1;
+    @cb;
+    @cb;
+
+    cpuif.assert_read('h0, 'b00);
+    cpuif.assert_read('h4, 'h00);
+
+    cpuif.write('h0, 'b11);
+    cpuif.write('h0, 'b11);
+    cpuif.write('h0, 'b11);
+    cpuif.assert_read('h0, 'h00);
+    cpuif.assert_read('h4, 'h03);
+
+{% endblock %}

test/test_precedence/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()