Add counter support

test/lib/cpuifs/apb3/apb3_intf_driver.sv

@@ -91,9 +91,10 @@ interface apb3_intf_driver #(
         reset();
     endtask
 
-    task assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data);
+    task assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
         logic [DATA_WIDTH-1:0] data;
         read(addr, data);
+        data &= mask;
         assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
     endtask
 

test/lib/simulators/modelsim.py

@@ -9,6 +9,8 @@ class ModelSim(Simulator):
         cmd = [
             "vlog", "-sv", "-quiet", "-l", "build.log",
 
+            "+incdir+%s" % os.path.join(os.path.dirname(__file__), ".."),
+
             # Free version of ModelSim throws errors if generate/endgenerate
             # blocks are not used.
             # These have been made optional long ago. Modern versions of SystemVerilog do

test/lib/simulators/xilinx.py

@@ -8,13 +8,14 @@ class Xilinx(Simulator):
     """
     Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
     As observed in v2021.1, clocking block assignments do not seem to actually simulate
-    correctly - assignemnt statements get ignored or the values get mangled.
+    correctly - assignment statements get ignored or the values get mangled.
 
     Keeping this here in case someday it works better...
     """
     def compile(self) -> None:
         cmd = [
-            "xvlog", "--sv"
+            "xvlog", "--sv",
+            "--include", os.path.join(os.path.dirname(__file__), ".."),
         ]
         cmd.extend(self.tb_files)
         subprocess.run(cmd, check=True)

test/lib/tb_base.sv

@@ -66,6 +66,7 @@ module tb;
         end
     end
 {%- endif %}
+    {% sv_line_anchor %}
 
     //--------------------------------------------------------------------------
     // Test Sequence
@@ -82,7 +83,7 @@ module tb;
             {%- endblock %}
             {%- endfilter %}
         end
-
+        {% sv_line_anchor %}
         ##5;
         $finish();
     end
@@ -90,7 +91,6 @@ module tb;
     //--------------------------------------------------------------------------
     // Monitor for timeout
     //--------------------------------------------------------------------------
-    {% sv_line_anchor %}
     initial begin
         ##{{cls.timeout_clk_cycles}};
         $fatal(1, "Test timed out after {{cls.timeout_clk_cycles}} clock cycles");

test/test_bitwise_reduce/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_counter_basics/regblock.rdl

@@ -0,0 +1,68 @@
+addrmap top {
+    reg {
+        field {
+            sw=r; hw=na; counter;
+        } implied_up[3:0] = 0xD;
+        field {
+            sw=r; hw=na; counter;
+            incrvalue=1;
+        } up[7:4] = 0xD;
+        field {
+            sw=r; hw=na; counter;
+            decrvalue=1;
+        } down[11:8] = 0x4;
+        field {
+            sw=r; hw=na; counter;
+            incrvalue=1;
+            decrvalue=1;
+        } updown[15:12] = 0;
+
+        field {
+            sw=r; hw=na; counter;
+            incrvalue=3;
+            decrvalue=3;
+        } updown2[19:16] = 0;
+
+        field {
+            sw=r; hw=na; counter;
+            incrwidth=2;
+            decrwidth=2;
+        } updown3[23:20] = 0;
+
+        field {
+            sw=r; hw=na; counter;
+        } updown4[27:24] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } step[29:28] = 0;
+        updown4->incrvalue = step;
+        updown4->decrvalue = step;
+
+        field {
+            sw=w; hw=r; singlepulse;
+        } do_count_up[30:30] = 0;
+        field {
+            sw=w; hw=r; singlepulse;
+        } do_count_down[31:31] = 0;
+        updown2->incr = do_count_up;
+        updown2->decr = do_count_down;
+        updown3->incr = do_count_up;
+        updown3->decr = do_count_down;
+        updown4->incr = do_count_up;
+        updown4->decr = do_count_down;
+    } simple @ 0x0;
+
+
+    reg {
+        field {
+            sw=r; hw=na; rclr; counter;
+        } overflow_count[8] = 0;
+
+        field {
+            sw=r; hw=na; rclr; counter;
+        } underflow_count[8] = 0;
+    } wrap_counter @ 0x4;
+    wrap_counter.overflow_count->incr = simple.updown3->overflow;
+    wrap_counter.underflow_count->incr = simple.updown3->underflow;
+};

test/test_counter_basics/tb_template.sv

@@ -0,0 +1,93 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    //--------------------------------------------------------------------------
+    // Test simple counters
+    //--------------------------------------------------------------------------
+    // up
+    cpuif.assert_read('h0, 'hD, 'h000F);
+    cb.hwif_in.simple.implied_up.incr <= '1;
+    repeat(4) @cb;
+    cb.hwif_in.simple.implied_up.incr <= '0;
+    cpuif.assert_read('h0, 'h1, 'h000F);
+
+    // up
+    cpuif.assert_read('h0, 'hD0, 'h00F0);
+    cb.hwif_in.simple.up.incr <= '1;
+    repeat(4) @cb;
+    cb.hwif_in.simple.up.incr <= '0;
+    cpuif.assert_read('h0, 'h10, 'h00F0);
+
+    // down
+    cpuif.assert_read('h0, 'h400, 'h0F00);
+    cb.hwif_in.simple.down.decr <= '1;
+    repeat(6) @cb;
+    cb.hwif_in.simple.down.decr <= '0;
+    cpuif.assert_read('h0, 'hE00, 'h0F00);
+
+    // up/down via hw
+    cpuif.assert_read('h0, 'h0000, 'hF000);
+    cb.hwif_in.simple.updown.incr <= '1;
+    repeat(6) @cb;
+    cb.hwif_in.simple.updown.incr <= '0;
+    cpuif.assert_read('h0, 'h6000, 'hF000);
+    cb.hwif_in.simple.updown.decr <= '1;
+    repeat(6) @cb;
+    cb.hwif_in.simple.updown.decr <= '0;
+    cpuif.assert_read('h0, 'h0000, 'hF000);
+    cb.hwif_in.simple.updown.decr <= '1;
+    repeat(6) @cb;
+    cb.hwif_in.simple.updown.decr <= '0;
+    cpuif.assert_read('h0, 'hA000, 'hF000);
+    cb.hwif_in.simple.updown.incr <= '1;
+    repeat(6) @cb;
+    cb.hwif_in.simple.updown.incr <= '0;
+    cpuif.assert_read('h0, 'h0000, 'hF000);
+
+    // up/down via sw
+    cpuif.assert_read('h0, 'h00000, 'hF0000);
+    repeat(3) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'h90000, 'hF0000);
+    repeat(3) cpuif.write('h0, 'h8000_0000); // decr
+    cpuif.assert_read('h0, 'h00000, 'hF0000);
+    repeat(3) cpuif.write('h0, 'h8000_0000); // decr
+    cpuif.assert_read('h0, 'h70000, 'hF0000);
+    repeat(3) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'h00000, 'hF0000);
+
+    // up/down via hw + external dynamic stepsize
+    cpuif.assert_read('h0, 'h000000, 'hF00000);
+    cb.hwif_in.simple.updown3.incrvalue <= 'h2;
+    repeat(3) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'h600000, 'hF00000);
+    cpuif.assert_read('h4, 'h00_00); // no overflows or underflows
+    cb.hwif_in.simple.updown3.decrvalue <= 'h3;
+    repeat(3) cpuif.write('h0, 'h8000_0000); // decr
+    cpuif.assert_read('h0, 'hD00000, 'hF00000);
+    cpuif.assert_read('h4, 'h01_00); // one underflow
+    cb.hwif_in.simple.updown3.incrvalue <= 'h1;
+    repeat(2) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'hF00000, 'hF00000);
+    cpuif.assert_read('h4, 'h00_00); // no overflows or underflows
+    repeat(1) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'h000000, 'hF00000);
+    cpuif.assert_read('h4, 'h00_01); // one overflow
+    repeat(32) cpuif.write('h0, 'h4000_0000); // incr
+    cpuif.assert_read('h0, 'h000000, 'hF00000);
+    cpuif.assert_read('h4, 'h00_02); // overflow
+
+    // up/down via hw + referenced dynamic stepsize
+    cpuif.assert_read('h0, 'h0000000, 'hF000000);
+    repeat(4) cpuif.write('h0, 'h4000_0000 + (2'h3 << 28)); // + 3
+    cpuif.assert_read('h0, 'hC000000, 'hF000000);
+    repeat(4) cpuif.write('h0, 'h8000_0000 + (2'h1 << 28)); // - 1
+    cpuif.assert_read('h0, 'h8000000, 'hF000000);
+    repeat(2) cpuif.write('h0, 'h8000_0000 + (2'h3 << 28)); // - 3
+    cpuif.assert_read('h0, 'h2000000, 'hF000000);
+
+{% endblock %}

test/test_counter_basics/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.regblock_testcase import RegblockTestCase
+
+class Test(RegblockTestCase):
+    def test_dut(self):
+        self.run_test()

test/test_counter_saturate/regblock.rdl

@@ -0,0 +1,88 @@
+addrmap top {
+    field strobe_t {
+        sw=w; hw=r; singlepulse;
+    };
+
+    reg {
+        field {
+            sw=r; hw=r; counter;
+            incrsaturate;
+            decrsaturate;
+        } count[8] = 0;
+
+        strobe_t increment[9:9] = 0;
+        strobe_t decrement[10:10] = 0;
+        strobe_t clear[11:11] = 0;
+        strobe_t set[12:12] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } step[23:16] = 1;
+
+        count->incr = increment;
+        count->decr = decrement;
+        count->hwclr = clear;
+        count->hwset = set;
+        count->incrvalue = step;
+        count->decrvalue = step;
+    } saturate_via_bool @ 0x0;
+
+
+    reg {
+        field {
+            sw=r; hw=r; counter;
+            incrsaturate = 250;
+            decrsaturate = 5;
+        } count[8] = 0;
+
+        strobe_t increment[9:9] = 0;
+        strobe_t decrement[10:10] = 0;
+        strobe_t clear[11:11] = 0;
+        strobe_t set[12:12] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } step[23:16] = 1;
+
+        count->incr = increment;
+        count->decr = decrement;
+        count->hwclr = clear;
+        count->hwset = set;
+        count->incrvalue = step;
+        count->decrvalue = step;
+    } saturate_via_const @ 0x4;
+
+
+    reg {
+        field {
+            sw=r; hw=r; counter;
+        } count[8] = 0;
+
+        strobe_t increment[9:9] = 0;
+        strobe_t decrement[10:10] = 0;
+        strobe_t clear[11:11] = 0;
+        strobe_t set[12:12] = 0;
+
+        field {
+            sw=rw; hw=na;
+        } step[23:16] = 1;
+
+        count->incr = increment;
+        count->decr = decrement;
+        count->hwclr = clear;
+        count->hwset = set;
+        count->incrvalue = step;
+        count->decrvalue = step;
+    } saturate_via_ref @ 0x8;
+
+    reg {
+        field {
+            sw=rw; hw=na;
+        } min[8] = 0x00;
+        field {
+            sw=rw; hw=na;
+        } max[8] = 0xFF;
+    } saturate_control @ 0xC;
+    saturate_via_ref.count -> decrsaturate = saturate_control.min;
+    saturate_via_ref.count -> incrsaturate = saturate_control.max;
+};

test/test_counter_saturate/tb_template.sv

@@ -0,0 +1,214 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // counter controls are the same for each sub-test
+    `define incr (1<<9)
+    `define decr (1<<10)
+    `define clr (1<<11)
+    `define set (1<<12)
+    `define step(n) (n<<16)
+
+    //--------------------------------------------------------------------------
+    // Test incrsaturate = true; decrsaturate = true;
+    //--------------------------------------------------------------------------
+    cpuif.assert_read('h0, 'h00, 'hFF);
+
+    // incrsaturate via +1
+    cpuif.write('h0, `set);
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+    cpuif.write('h0, `decr + `step(1));
+    cpuif.assert_read('h0, 'hFE, 'hFF);
+    cpuif.write('h0, `incr + `step(1));
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+    cpuif.write('h0, `incr + `step(1));
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+
+    // decrsaturate via +1
+    cpuif.write('h0, `clr);
+    cpuif.assert_read('h0, 'h00, 'hFF);
+    cpuif.write('h0, `incr + `step(1));
+    cpuif.assert_read('h0, 'h01, 'hFF);
+    cpuif.write('h0, `decr + `step(1));
+    cpuif.assert_read('h0, 'h00, 'hFF);
+    cpuif.write('h0, `decr + `step(1));
+    cpuif.assert_read('h0, 'h00, 'hFF);
+
+    // incrsaturate via larger steps
+    cpuif.write('h0, `set);
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+    cpuif.write('h0, `decr + `step(1));
+    cpuif.assert_read('h0, 'hFE, 'hFF);
+    cpuif.write('h0, `incr + `step(2));
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+    cpuif.write('h0, `incr + `step(3));
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+    cpuif.write('h0, `incr + `step(255));
+    cpuif.assert_read('h0, 'hFF, 'hFF);
+
+    // decrsaturate via larger steps
+    cpuif.write('h0, `clr);
+    cpuif.assert_read('h0, 'h00, 'hFF);
+    cpuif.write('h0, `incr + `step(1));
+    cpuif.assert_read('h0, 'h01, 'hFF);
+    cpuif.write('h0, `decr + `step(2));
+    cpuif.assert_read('h0, 'h00, 'hFF);
+    cpuif.write('h0, `decr + `step(3));
+    cpuif.assert_read('h0, 'h00, 'hFF);
+    cpuif.write('h0, `decr + `step(255));
+    cpuif.assert_read('h0, 'h00, 'hFF);
+
+    //--------------------------------------------------------------------------
+    // Test incrsaturate = 250; decrsaturate = 5;
+    //--------------------------------------------------------------------------
+    cpuif.assert_read('h4, 'h05, 'hFF);
+
+    // incrsaturate via +1
+    cpuif.write('h4, `set);
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+    cpuif.write('h4, `decr + `step(1));
+    cpuif.assert_read('h4, 'hF9, 'hFF);
+    cpuif.write('h4, `incr + `step(1));
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+    cpuif.write('h4, `incr + `step(1));
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+
+    // decrsaturate via +1
+    cpuif.write('h4, `clr);
+    cpuif.assert_read('h4, 'h05, 'hFF);
+    cpuif.write('h4, `incr + `step(1));
+    cpuif.assert_read('h4, 'h06, 'hFF);
+    cpuif.write('h4, `decr + `step(1));
+    cpuif.assert_read('h4, 'h05, 'hFF);
+    cpuif.write('h4, `decr + `step(1));
+    cpuif.assert_read('h4, 'h05, 'hFF);
+
+    // incrsaturate via larger steps
+    cpuif.write('h4, `set);
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+    cpuif.write('h4, `decr + `step(1));
+    cpuif.assert_read('h4, 'hF9, 'hFF);
+    cpuif.write('h4, `incr + `step(2));
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+    cpuif.write('h4, `incr + `step(3));
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+    cpuif.write('h4, `incr + `step(255));
+    cpuif.assert_read('h4, 'hFA, 'hFF);
+
+    // decrsaturate via larger steps
+    cpuif.write('h4, `clr);
+    cpuif.assert_read('h4, 'h05, 'hFF);
+    cpuif.write('h4, `incr + `step(1));
+    cpuif.assert_read('h4, 'h06, 'hFF);
+    cpuif.write('h4, `decr + `step(2));
+    cpuif.assert_read('h4, 'h05, 'hFF);
+    cpuif.write('h4, `decr + `step(3));
+    cpuif.assert_read('h4, 'h05, 'hFF);
+    cpuif.write('h4, `decr + `step(255));
+    cpuif.assert_read('h4, 'h05, 'hFF);
+
+    //--------------------------------------------------------------------------
+    // Test incrsaturate = <ref 255>; decrsaturate = <ref 0>;
+    //--------------------------------------------------------------------------
+    cpuif.assert_read('h8, 'h00, 'hFF);
+
+    // incrsaturate via +1
+    cpuif.write('h8, `set);
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'hFE, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+
+    // decrsaturate via +1
+    cpuif.write('h8, `clr);
+    cpuif.assert_read('h8, 'h00, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'h01, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'h00, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'h00, 'hFF);
+
+    // incrsaturate via larger steps
+    cpuif.write('h8, `set);
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'hFE, 'hFF);
+    cpuif.write('h8, `incr + `step(2));
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+    cpuif.write('h8, `incr + `step(3));
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+    cpuif.write('h8, `incr + `step(255));
+    cpuif.assert_read('h8, 'hFF, 'hFF);
+
+    // decrsaturate via larger steps
+    cpuif.write('h8, `clr);
+    cpuif.assert_read('h8, 'h00, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'h01, 'hFF);
+    cpuif.write('h8, `decr + `step(2));
+    cpuif.assert_read('h8, 'h00, 'hFF);
+    cpuif.write('h8, `decr + `step(3));
+    cpuif.assert_read('h8, 'h00, 'hFF);
+    cpuif.write('h8, `decr + `step(255));
+    cpuif.assert_read('h8, 'h00, 'hFF);
+
+    //--------------------------------------------------------------------------
+    // Test incrsaturate = <ref 250>; decrsaturate = <ref 5>;
+    //--------------------------------------------------------------------------
+    cpuif.write('hc, 'hFA_05);
+
+    cpuif.assert_read('h4, 'h05, 'hFF);
+
+    // incrsaturate via +1
+    cpuif.write('h8, `set);
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'hF9, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+
+    // decrsaturate via +1
+    cpuif.write('h8, `clr);
+    cpuif.assert_read('h8, 'h05, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'h06, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'h05, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'h05, 'hFF);
+
+    // incrsaturate via larger steps
+    cpuif.write('h8, `set);
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+    cpuif.write('h8, `decr + `step(1));
+    cpuif.assert_read('h8, 'hF9, 'hFF);
+    cpuif.write('h8, `incr + `step(2));
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+    cpuif.write('h8, `incr + `step(3));
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+    cpuif.write('h8, `incr + `step(255));
+    cpuif.assert_read('h8, 'hFA, 'hFF);
+
+    // decrsaturate via larger steps
+    cpuif.write('h8, `clr);
+    cpuif.assert_read('h8, 'h05, 'hFF);
+    cpuif.write('h8, `incr + `step(1));
+    cpuif.assert_read('h8, 'h06, 'hFF);
+    cpuif.write('h8, `decr + `step(2));
+    cpuif.assert_read('h8, 'h05, 'hFF);
+    cpuif.write('h8, `decr + `step(3));
+    cpuif.assert_read('h8, 'h05, 'hFF);
+    cpuif.write('h8, `decr + `step(255));
+    cpuif.assert_read('h8, 'h05, 'hFF);
+
+{% endblock %}

test/test_counter_saturate/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.regblock_testcase import RegblockTestCase
+
+class Test(RegblockTestCase):
+    def test_dut(self):
+        self.run_test()

test/test_field_types/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_hw_access/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_onread_onwrite/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_read_fanin/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {%- block declarations %}
     {% sv_line_anchor %}

test/test_singlepulse/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_structural_sw_rw/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_swacc_swmod/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}

test/test_swwe/tb_template.sv

@@ -1,4 +1,4 @@
-{% extends "lib/templates/tb_base.sv" %}
+{% extends "lib/tb_base.sv" %}
 
 {% block seq %}
     {% sv_line_anchor %}