bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

doc tweaks

Browse Source
This commit is contained in:
Alex Mykyta
2022-02-28 22:10:09 -08:00
parent 9295cbb7c0
commit a8bf3c5132
3 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@@ -3,7 +3,7 @@
[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)
# PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
## Documentation
See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details