doc tweaks

2022-02-28 22:10:09 -08:00
parent 9295cbb7c0
commit a8bf3c5132
3 changed files with 3 additions and 2 deletions
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -10,6 +10,7 @@ your hardware design.
 * Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
 * Configurable pipelining options for designs with fast clock rates.
 * Broad support for SystemRDL 2.0 features
+* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus