doc tweaks

2022-02-28 22:10:09 -08:00
parent 9295cbb7c0
commit a8bf3c5132
3 changed files with 3 additions and 2 deletions
--- a/setup.py
+++ b/setup.py
@@ -15,7 +15,7 @@ setuptools.setup(
    version=version,
    author="Alex Mykyta",
    author_email="amykyta3@github.com",
-    description="Convert SystemRDL into SystemVerilog RTL that implements a register block",
+    description="Compile SystemRDL into a SystemVerilog control/status register (CSR) block",
    long_description=long_description,
    long_description_content_type="text/markdown",
    url="https://github.com/SystemRDL/PeakRDL-regblock",