bslathi19/PeakRDL-regblock
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Alex Mykyta
2022-02-28 22:10:09 -08:00
parent 9295cbb7c0
commit a8bf3c5132
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README.md
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[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock) [![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)
# PeakRDL-regblock # PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input. Compile SystemRDL into a SystemVerilog control/status register (CSR) block
## Documentation ## Documentation
See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details

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docs/index.rst
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* Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more) * Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
* Configurable pipelining options for designs with fast clock rates. * Configurable pipelining options for designs with fast clock rates.
* Broad support for SystemRDL 2.0 features * Broad support for SystemRDL 2.0 features
* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus

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setup.py
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version=version, version=version,
author="Alex Mykyta", author="Alex Mykyta",
author_email="amykyta3@github.com", author_email="amykyta3@github.com",
description="Convert SystemRDL into SystemVerilog RTL that implements a register block", description="Compile SystemRDL into a SystemVerilog control/status register (CSR) block",
long_description=long_description, long_description=long_description,
long_description_content_type="text/markdown", long_description_content_type="text/markdown",
url="https://github.com/SystemRDL/PeakRDL-regblock", url="https://github.com/SystemRDL/PeakRDL-regblock",