bslathi19/PeakRDL-regblock
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This commit is contained in:
Alex Mykyta
2025-10-13 22:42:40 -07:00
parent a440cc1976
commit b097062e85
5 changed files with 7 additions and 10 deletions
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2
src/peakrdl_regblock/addr_decode.py
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@@ -194,7 +194,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
n_subwords = regwidth // accesswidth
subword_stride = accesswidth // 8
for i in range(n_subwords):
rhs = f"cpuif_req_masked & (cpuif_addr == {self._get_address_str(node, subword_offset=(i*subword_stride))})"
rhs = f"cpuif_req_masked & (cpuif_addr == {self._get_address_str(node, subword_offset=i*subword_stride)})"
s = f"{self.addr_decode.get_access_strobe(node)}[{i}] = {rhs};"
self.add_content(s)
if node.external:

2
src/peakrdl_regblock/field_logic/hw_interrupts_with_write.py
View File

@@ -50,7 +50,7 @@ class StickyWEL(Sticky, WELWrite):
class StickybitWE(Stickybit, WEWrite):
"""
Normal stickybiti with write enable
Normal stickybit with write enable
"""
comment = "stickybit with WE"
def is_match(self, field: 'FieldNode') -> bool: