bslathi19/PeakRDL-regblock
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more field logic

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This commit is contained in:
Alex Mykyta
2021-10-28 22:34:29 -07:00
parent f473dfb9e7
commit d5c5d42390
23 changed files with 488 additions and 264 deletions
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6
peakrdl/regblock/cpuif/base.py
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@@ -9,8 +9,8 @@ if TYPE_CHECKING:
class CpuifBase:
template_path = "cpuif/base_tmpl.sv"
def __init__(self, exporter:'RegblockExporter', cpuif_reset:'SignalBase', data_width:int=32, addr_width:int=32):
self.exporter = exporter
def __init__(self, exp:'RegblockExporter', cpuif_reset:'SignalBase', data_width:int=32, addr_width:int=32):
self.exp = exp
self.cpuif_reset = cpuif_reset
self.data_width = data_width
self.addr_width = addr_width
@@ -28,5 +28,5 @@ class CpuifBase:
"get_always_ff_event": get_always_ff_event,
}
template = self.exporter.jj_env.get_template(self.template_path)
template = self.exp.jj_env.get_template(self.template_path)
return template.render(context)