Add AXI4-Lite CPUIF

peakrdl/regblock/cpuif/axi4lite/__init__.py

@@ -0,0 +1,49 @@
+from ..base import CpuifBase
+
+class AXI4Lite_Cpuif(CpuifBase):
+    template_path = "cpuif/axi4lite/axi4lite_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "axi4lite_intf.slave s_axil"
+
+    def signal(self, name:str) -> str:
+        return "s_axil." + name.upper()
+
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
+
+class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "output logic " + self.signal("awready"),
+            "input wire " + self.signal("awvalid"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("awaddr"),
+            "input wire [2:0] " + self.signal("awprot"),
+
+            "output logic " + self.signal("wready"),
+            "input wire " + self.signal("wvalid"),
+            f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
+            f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
+
+            "input wire " + self.signal("bready"),
+            "output logic " + self.signal("bvalid"),
+            "output logic [1:0] " + self.signal("bresp"),
+
+            "output logic " + self.signal("arready"),
+            "input wire " + self.signal("arvalid"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("araddr"),
+            "input wire [2:0] " + self.signal("arprot"),
+
+            "input wire " + self.signal("rready"),
+            "output logic " + self.signal("rvalid"),
+            f"output logic [{self.data_width-1}:0] " + self.signal("rdata"),
+            "output logic [1:0] " + self.signal("rresp"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "s_axil_" + name

peakrdl/regblock/cpuif/axi4lite/axi4lite_tmpl.sv

@@ -0,0 +1,102 @@
+enum logic [1:0] {
+    CPUIF_IDLE,
+    CPUIF_BRESP,
+    CPUIF_RRESP
+} cpuif_state;
+
+logic cpuif_prev_was_rd;
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        cpuif_state <= CPUIF_IDLE;
+        cpuif_prev_was_rd <= '0;
+
+        cpuif_req <= '0;
+        cpuif_req_is_wr <= '0;
+        cpuif_addr <= '0;
+        cpuif_wr_data <= '0;
+
+        {{cpuif.signal("arready")}} <= '0;
+        {{cpuif.signal("awready")}} <= '0;
+        {{cpuif.signal("wready")}} <= '0;
+        {{cpuif.signal("bvalid")}} <= '0;
+        {{cpuif.signal("bresp")}} <= '0;
+        {{cpuif.signal("rvalid")}} <= '0;
+        {{cpuif.signal("rdata")}} <= '0;
+        {{cpuif.signal("rresp")}} <= '0;
+    end else begin
+        // Load response transfers as they arrive
+        if(cpuif_rd_ack) begin
+            {{cpuif.signal("rvalid")}} <= '1;
+            {{cpuif.signal("rdata")}} <= cpuif_rd_data;
+            if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
+            else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
+        end
+        if(cpuif_wr_ack) begin
+            {{cpuif.signal("bvalid")}} <= '1;
+            if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
+            else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
+        end
+
+        // Transaction state machine
+        case(cpuif_state)
+            CPUIF_IDLE: begin
+                // round-robin arbitrate between read/write requests
+                // Allow read if previous transfer was not a read, or no write is active
+                if({{cpuif.signal("arvalid")}} && (!cpuif_prev_was_rd || !{{cpuif.signal("awvalid")}} || !{{cpuif.signal("wvalid")}})) begin
+                    cpuif_req <= '1;
+                    cpuif_req_is_wr <= '0;
+                    {%- if cpuif.data_width == 8 %}
+                    cpuif_addr <= {{cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:0];
+                    {%- else %}
+                    cpuif_addr <= { {{-cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+                    {%- endif %}
+                    {{cpuif.signal("arready")}} <= '1;
+                    cpuif_state <= CPUIF_RRESP;
+                end else if({{cpuif.signal("awvalid")}} && {{cpuif.signal("wvalid")}}) begin
+                    {{cpuif.signal("awready")}} <= '1;
+                    {{cpuif.signal("wready")}} <= '1;
+                    if({{cpuif.signal("wstrb")}} != {{"%d'b" % cpuif.data_width_bytes}}{{"1" * cpuif.data_width_bytes}}) begin
+                        // Unaligned writes or use of byte strobes is not supported yet
+                        {{cpuif.signal("bvalid")}} <= '1;
+                        {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
+                    end else begin
+                        cpuif_req <= '1;
+                        cpuif_req_is_wr <= '1;
+                        {%- if cpuif.data_width == 8 %}
+                        cpuif_addr <= {{cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:0];
+                        {%- else %}
+                        cpuif_addr <= { {{-cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+                        {%- endif %}
+                        cpuif_wr_data <= {{cpuif.signal("wdata")}};
+                    end
+                    cpuif_state <= CPUIF_BRESP;
+                end
+            end
+
+            CPUIF_BRESP: begin
+                cpuif_req <= '0;
+                {{cpuif.signal("awready")}} <= '0;
+                {{cpuif.signal("wready")}} <= '0;
+                cpuif_prev_was_rd <= '0;
+                if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
+                    {{cpuif.signal("bvalid")}} <= '0;
+                    cpuif_state <= CPUIF_IDLE;
+                end
+            end
+
+            CPUIF_RRESP: begin
+                cpuif_req <= '0;
+                {{cpuif.signal("arready")}} <= '0;
+                cpuif_prev_was_rd <= '1;
+                if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
+                    {{cpuif.signal("rvalid")}} <= '0;
+                    cpuif_state <= CPUIF_IDLE;
+                end
+            end
+
+            default: begin
+                cpuif_state <= CPUIF_IDLE;
+            end
+        endcase
+    end
+end