Add AXI4-Lite CPUIF
This commit is contained in:
Alex Mykyta
49
peakrdl/regblock/cpuif/axi4lite/__init__.py
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49
peakrdl/regblock/cpuif/axi4lite/__init__.py
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@@ -0,0 +1,49 @@
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from ..base import CpuifBase
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class AXI4Lite_Cpuif(CpuifBase):
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template_path = "cpuif/axi4lite/axi4lite_tmpl.sv"
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@property
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def port_declaration(self) -> str:
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return "axi4lite_intf.slave s_axil"
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def signal(self, name:str) -> str:
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return "s_axil." + name.upper()
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@property
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def data_width_bytes(self) -> int:
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return self.data_width // 8
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class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
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@property
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def port_declaration(self) -> str:
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lines = [
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"output logic " + self.signal("awready"),
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"input wire " + self.signal("awvalid"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("awaddr"),
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"input wire [2:0] " + self.signal("awprot"),
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"output logic " + self.signal("wready"),
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"input wire " + self.signal("wvalid"),
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f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
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f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
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"input wire " + self.signal("bready"),
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"output logic " + self.signal("bvalid"),
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"output logic [1:0] " + self.signal("bresp"),
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"output logic " + self.signal("arready"),
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"input wire " + self.signal("arvalid"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("araddr"),
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"input wire [2:0] " + self.signal("arprot"),
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"input wire " + self.signal("rready"),
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"output logic " + self.signal("rvalid"),
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f"output logic [{self.data_width-1}:0] " + self.signal("rdata"),
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"output logic [1:0] " + self.signal("rresp"),
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]
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return ",\n".join(lines)
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def signal(self, name:str) -> str:
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return "s_axil_" + name
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102
peakrdl/regblock/cpuif/axi4lite/axi4lite_tmpl.sv
Normal file
102
peakrdl/regblock/cpuif/axi4lite/axi4lite_tmpl.sv
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@@ -0,0 +1,102 @@
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enum logic [1:0] {
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CPUIF_IDLE,
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CPUIF_BRESP,
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CPUIF_RRESP
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} cpuif_state;
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logic cpuif_prev_was_rd;
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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cpuif_state <= CPUIF_IDLE;
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cpuif_prev_was_rd <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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{{cpuif.signal("arready")}} <= '0;
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{{cpuif.signal("awready")}} <= '0;
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{{cpuif.signal("wready")}} <= '0;
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{{cpuif.signal("bvalid")}} <= '0;
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{{cpuif.signal("bresp")}} <= '0;
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{{cpuif.signal("rvalid")}} <= '0;
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{{cpuif.signal("rdata")}} <= '0;
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{{cpuif.signal("rresp")}} <= '0;
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end else begin
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// Load response transfers as they arrive
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if(cpuif_rd_ack) begin
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{{cpuif.signal("rvalid")}} <= '1;
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{{cpuif.signal("rdata")}} <= cpuif_rd_data;
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if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
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end
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if(cpuif_wr_ack) begin
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{{cpuif.signal("bvalid")}} <= '1;
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if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
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end
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// Transaction state machine
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case(cpuif_state)
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CPUIF_IDLE: begin
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// round-robin arbitrate between read/write requests
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// Allow read if previous transfer was not a read, or no write is active
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if({{cpuif.signal("arvalid")}} && (!cpuif_prev_was_rd || !{{cpuif.signal("awvalid")}} || !{{cpuif.signal("wvalid")}})) begin
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cpuif_req <= '1;
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cpuif_req_is_wr <= '0;
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{%- if cpuif.data_width == 8 %}
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cpuif_addr <= {{cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:0];
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{%- else %}
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cpuif_addr <= { {{-cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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{{cpuif.signal("arready")}} <= '1;
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cpuif_state <= CPUIF_RRESP;
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end else if({{cpuif.signal("awvalid")}} && {{cpuif.signal("wvalid")}}) begin
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{{cpuif.signal("awready")}} <= '1;
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{{cpuif.signal("wready")}} <= '1;
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if({{cpuif.signal("wstrb")}} != {{"%d'b" % cpuif.data_width_bytes}}{{"1" * cpuif.data_width_bytes}}) begin
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// Unaligned writes or use of byte strobes is not supported yet
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{{cpuif.signal("bvalid")}} <= '1;
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{{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
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end else begin
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cpuif_req <= '1;
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cpuif_req_is_wr <= '1;
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{%- if cpuif.data_width == 8 %}
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cpuif_addr <= {{cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:0];
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{%- else %}
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cpuif_addr <= { {{-cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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cpuif_wr_data <= {{cpuif.signal("wdata")}};
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end
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cpuif_state <= CPUIF_BRESP;
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end
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end
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CPUIF_BRESP: begin
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cpuif_req <= '0;
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{{cpuif.signal("awready")}} <= '0;
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{{cpuif.signal("wready")}} <= '0;
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cpuif_prev_was_rd <= '0;
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if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
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{{cpuif.signal("bvalid")}} <= '0;
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cpuif_state <= CPUIF_IDLE;
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end
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end
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CPUIF_RRESP: begin
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cpuif_req <= '0;
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{{cpuif.signal("arready")}} <= '0;
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cpuif_prev_was_rd <= '1;
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if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
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{{cpuif.signal("rvalid")}} <= '0;
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cpuif_state <= CPUIF_IDLE;
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end
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end
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default: begin
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cpuif_state <= CPUIF_IDLE;
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end
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endcase
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end
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end
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14
test/lib/cpuifs/axi4lite/__init__.py
Normal file
14
test/lib/cpuifs/axi4lite/__init__.py
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@@ -0,0 +1,14 @@
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from ..base import CpuifTestMode
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from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flattened
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class AXI4Lite(CpuifTestMode):
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cpuif_cls = AXI4Lite_Cpuif
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tb_files = [
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"axi4lite_intf.sv",
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"axi4lite_intf_driver.sv",
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]
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tb_template = "tb_inst.sv"
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class FlatAXI4Lite(AXI4Lite):
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cpuif_cls = AXI4Lite_Cpuif_flattened
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80
test/lib/cpuifs/axi4lite/axi4lite_intf.sv
Normal file
80
test/lib/cpuifs/axi4lite/axi4lite_intf.sv
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@@ -0,0 +1,80 @@
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interface axi4lite_intf #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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);
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logic AWREADY;
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logic AWVALID;
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logic [ADDR_WIDTH-1:0] AWADDR;
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logic [2:0] AWPROT;
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logic WREADY;
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logic WVALID;
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logic [DATA_WIDTH-1:0] WDATA;
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logic [DATA_WIDTH/8-1:0] WSTRB;
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logic BREADY;
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logic BVALID;
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logic [1:0] BRESP;
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logic ARREADY;
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logic ARVALID;
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logic [ADDR_WIDTH-1:0] ARADDR;
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logic [2:0] ARPROT;
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logic RREADY;
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logic RVALID;
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logic [DATA_WIDTH-1:0] RDATA;
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logic [1:0] RRESP;
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modport master (
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input AWREADY,
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output AWVALID,
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output AWADDR,
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output AWPROT,
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input WREADY,
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output WVALID,
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output WDATA,
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output WSTRB,
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output BREADY,
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input BVALID,
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input BRESP,
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input ARREADY,
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output ARVALID,
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output ARADDR,
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output ARPROT,
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output RREADY,
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input RVALID,
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input RDATA,
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input RRESP
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);
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modport slave (
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output AWREADY,
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input AWVALID,
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input AWADDR,
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input AWPROT,
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output WREADY,
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input WVALID,
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input WDATA,
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input WSTRB,
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input BREADY,
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output BVALID,
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output BRESP,
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output ARREADY,
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input ARVALID,
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input ARADDR,
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input ARPROT,
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input RREADY,
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output RVALID,
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output RDATA,
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output RRESP
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);
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endinterface
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175
test/lib/cpuifs/axi4lite/axi4lite_intf_driver.sv
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175
test/lib/cpuifs/axi4lite/axi4lite_intf_driver.sv
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@@ -0,0 +1,175 @@
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interface axi4lite_intf_driver #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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)(
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input wire clk,
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input wire rst,
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axi4lite_intf.master m_axil
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);
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timeunit 1ps;
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timeprecision 1ps;
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logic AWREADY;
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logic AWVALID;
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logic [ADDR_WIDTH-1:0] AWADDR;
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logic [2:0] AWPROT;
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logic WREADY;
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logic WVALID;
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logic [DATA_WIDTH-1:0] WDATA;
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logic [DATA_WIDTH/8-1:0] WSTRB;
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logic BREADY;
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logic BVALID;
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logic [1:0] BRESP;
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logic ARREADY;
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logic ARVALID;
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logic [ADDR_WIDTH-1:0] ARADDR;
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logic [2:0] ARPROT;
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logic RREADY;
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logic RVALID;
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logic [DATA_WIDTH-1:0] RDATA;
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logic [1:0] RRESP;
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assign AWREADY = m_axil.AWREADY;
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assign m_axil.AWVALID = AWVALID;
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assign m_axil.AWADDR = AWADDR;
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assign m_axil.AWPROT = AWPROT;
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assign WREADY = m_axil.WREADY;
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assign m_axil.WVALID = WVALID;
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assign m_axil.WDATA = WDATA;
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assign m_axil.WSTRB = WSTRB;
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assign m_axil.BREADY = BREADY;
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assign BVALID = m_axil.BVALID;
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assign BRESP = m_axil.BRESP;
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assign ARREADY = m_axil.ARREADY;
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assign m_axil.ARVALID = ARVALID;
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assign m_axil.ARADDR = ARADDR;
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assign m_axil.ARPROT = ARPROT;
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assign m_axil.RREADY = RREADY;
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assign RVALID = m_axil.RVALID;
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assign RDATA = m_axil.RDATA;
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assign RRESP = m_axil.RRESP;
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default clocking cb @(posedge clk);
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default input #1step output #1;
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input AWREADY;
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output AWVALID;
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output AWADDR;
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output AWPROT;
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input WREADY;
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output WVALID;
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output WDATA;
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output WSTRB;
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inout BREADY;
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input BVALID;
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input BRESP;
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input ARREADY;
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output ARVALID;
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output ARADDR;
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output ARPROT;
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inout RREADY;
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input RVALID;
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input RDATA;
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input RRESP;
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endclocking
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task reset();
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cb.AWVALID <= '0;
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cb.AWADDR <= '0;
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cb.AWPROT <= '0;
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cb.WVALID <= '0;
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cb.WDATA <= '0;
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cb.WSTRB <= '0;
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cb.ARVALID <= '0;
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cb.ARADDR <= '0;
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cb.ARPROT <= '0;
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endtask
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initial forever begin
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cb.RREADY <= $urandom_range(1, 0);
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cb.BREADY <= $urandom_range(1, 0);
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@cb;
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end
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task write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data);
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bit w_before_aw;
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w_before_aw = $urandom_range(1,0);
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##0;
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fork
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begin
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if(w_before_aw) repeat($urandom_range(2,0)) @cb;
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cb.AWVALID <= '1;
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cb.AWADDR <= addr;
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cb.AWPROT <= '0;
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@(cb);
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while(cb.AWREADY !== 1'b1) @(cb);
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cb.AWVALID <= '0;
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end
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begin
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if(!w_before_aw) repeat($urandom_range(2,0)) @cb;
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cb.WVALID <= '1;
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cb.WDATA <= data;
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cb.WSTRB <= '1; // TODO: Support byte strobes
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@(cb);
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while(cb.WREADY !== 1'b1) @(cb);
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cb.WVALID <= '0;
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cb.WSTRB <= '0;
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end
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begin
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while(cb.BREADY !== 1'b1 && cb.BVALID !== 1'b1) @(cb);
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assert(!$isunknown(cb.BRESP)) else $error("Read from 0x%0x returned X's on BRESP", addr);
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end
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join
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endtask
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task read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
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##0;
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fork
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begin
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cb.ARVALID <= '1;
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cb.ARADDR <= addr;
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cb.ARPROT <= '0;
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@(cb);
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while(cb.ARREADY !== 1'b1) @(cb);
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cb.ARVALID <= '0;
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end
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begin
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@cb;
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while(!(cb.RREADY === 1'b1 && cb.RVALID === 1'b1)) @(cb);
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assert(!$isunknown(cb.RDATA)) else $error("Read from 0x%0x returned X's on RDATA", addr);
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assert(!$isunknown(cb.RRESP)) else $error("Read from 0x%0x returned X's on RRESP", addr);
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data = cb.RDATA;
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end
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join
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endtask
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task assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
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logic [DATA_WIDTH-1:0] data;
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read(addr, data);
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data &= mask;
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assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
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endtask
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initial begin
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reset();
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end
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initial forever begin
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@cb;
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if(!rst) assert(!$isunknown(cb.AWREADY)) else $error("Saw X on AWREADY!");
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if(!rst) assert(!$isunknown(cb.WREADY)) else $error("Saw X on WREADY!");
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if(!rst) assert(!$isunknown(cb.BVALID)) else $error("Saw X on BVALID!");
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if(!rst) assert(!$isunknown(cb.ARREADY)) else $error("Saw X on ARREADY!");
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if(!rst) assert(!$isunknown(cb.RVALID)) else $error("Saw X on RVALID!");
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end
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endinterface
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54
test/lib/cpuifs/axi4lite/tb_inst.sv
Normal file
54
test/lib/cpuifs/axi4lite/tb_inst.sv
Normal file
@@ -0,0 +1,54 @@
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{% sv_line_anchor %}
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axi4lite_intf #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) s_axil();
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axi4lite_intf_driver #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) cpuif (
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.clk(clk),
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.rst(rst),
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.m_axil(s_axil)
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);
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{% if type(cpuif).__name__.startswith("Flat") %}
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{% sv_line_anchor %}
|
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wire s_axil_awready;
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wire s_axil_awvalid;
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wire [{{exporter.cpuif.addr_width - 1}}:0] s_axil_awaddr;
|
||||
wire [2:0] s_axil_awprot;
|
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wire s_axil_wready;
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wire s_axil_wvalid;
|
||||
wire [{{exporter.cpuif.data_width - 1}}:0] s_axil_wdata;
|
||||
wire [{{exporter.cpuif.data_width_bytes - 1}}:0] s_axil_wstrb;
|
||||
wire s_axil_bready;
|
||||
wire s_axil_bvalid;
|
||||
wire [1:0] s_axil_bresp;
|
||||
wire s_axil_arready;
|
||||
wire s_axil_arvalid;
|
||||
wire [{{exporter.cpuif.addr_width - 1}}:0] s_axil_araddr;
|
||||
wire [2:0] s_axil_arprot;
|
||||
wire s_axil_rready;
|
||||
wire s_axil_rvalid;
|
||||
wire [{{exporter.cpuif.data_width - 1}}:0] s_axil_rdata;
|
||||
wire [1:0] s_axil_rresp;
|
||||
assign s_axil.AWREADY = s_axil_awready;
|
||||
assign s_axil_awvalid = s_axil.AWVALID;
|
||||
assign s_axil_awaddr = s_axil.AWADDR;
|
||||
assign s_axil_awprot = s_axil.AWPROT;
|
||||
assign s_axil.WREADY = s_axil_wready;
|
||||
assign s_axil_wvalid = s_axil.WVALID;
|
||||
assign s_axil_wdata = s_axil.WDATA;
|
||||
assign s_axil_wstrb = s_axil.WSTRB;
|
||||
assign s_axil_bready = s_axil.BREADY;
|
||||
assign s_axil.BVALID = s_axil_bvalid;
|
||||
assign s_axil.BRESP = s_axil_bresp;
|
||||
assign s_axil.ARREADY = s_axil_arready;
|
||||
assign s_axil_arvalid = s_axil.ARVALID;
|
||||
assign s_axil_araddr = s_axil.ARADDR;
|
||||
assign s_axil_arprot = s_axil.ARPROT;
|
||||
assign s_axil_rready = s_axil.RREADY;
|
||||
assign s_axil.RVALID = s_axil_rvalid;
|
||||
assign s_axil.RDATA = s_axil_rdata;
|
||||
assign s_axil.RRESP = s_axil_rresp;
|
||||
{% endif %}
|
||||
@@ -19,6 +19,12 @@ class ModelSim(Simulator):
|
||||
|
||||
# Ignore noisy warning about vopt-time checking of always_comb/always_latch
|
||||
"-suppress", "2583",
|
||||
|
||||
# all warnings are errors
|
||||
"-warning", "error",
|
||||
|
||||
# except this one.. TODO: figure out if I can avoid this
|
||||
"-suppress", "13314",
|
||||
]
|
||||
|
||||
# Add source files
|
||||
|
||||
@@ -1,12 +1,15 @@
|
||||
from itertools import product
|
||||
|
||||
from .cpuifs.apb3 import APB3, FlatAPB3
|
||||
from .cpuifs.axi4lite import AXI4Lite, FlatAXI4Lite
|
||||
from .cpuifs.passthrough import Passthrough
|
||||
|
||||
|
||||
all_cpuif = [
|
||||
APB3(),
|
||||
FlatAPB3(),
|
||||
AXI4Lite(),
|
||||
FlatAXI4Lite(),
|
||||
Passthrough(),
|
||||
]
|
||||
|
||||
|
||||
Reference in New Issue
Block a user