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Merge APB doc pages

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This commit is contained in:
Alex Mykyta
2022-09-15 21:18:06 -07:00
parent abf3b101d8
commit e46999fc1d
2 changed files with 38 additions and 13 deletions
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48
docs/cpuif/apb3.rst → docs/cpuif/apb.rst
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@@ -1,5 +1,24 @@
AMBA 3 APB AMBA APB
========== ========
Both APB3 and APB4 standards are supported.
.. warning::
Some IP vendors will incorrectly implement the address signalling
assuming word-addresses. (that each increment of ``PADDR`` is the next word)
For this exporter, values on the interface's ``PADDR`` input are interpreted
as byte-addresses. (an APB interface with 32-bit wide data increments
``PADDR`` in steps of 4 for every word). Even though APB protocol does not
allow for unaligned transfers, this is in accordance to the official AMBA
specification.
Be sure to double-check the interpretation of your interconnect IP. A simple
bit-shift operation can be used to correct this if necessary.
APB3
----
Implements the register block using an Implements the register block using an
`AMBA 3 APB <https://developer.arm.com/documentation/ihi0024/b/Introduction/About-the-AMBA-3-APB>`_ `AMBA 3 APB <https://developer.arm.com/documentation/ihi0024/b/Introduction/About-the-AMBA-3-APB>`_
@@ -18,14 +37,21 @@ Flattened inputs/outputs
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened` Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
.. warning:: APB4
Some IP vendors will incorrectly implement the address signalling ----
assuming word-addresses. (that each increment of ``PADDR`` is the next word)
For this exporter, values on the interface's ``PADDR`` input are interpreted Implements the register block using an
as byte-addresses. (a 32-bit APB bus increments ``PADDR`` in steps of 4) `AMBA 4 APB <https://developer.arm.com/documentation/ihi0024/d/?lang=en>`_
Although APB protocol does not allow for unaligned transfers, this is in CPU interface.
accordance to the official AMBA bus specification.
Be sure to double-check the interpretation of your interconnect IP. A simple The APB4 CPU interface comes in two i/o port flavors:
bit-shift operation can be used to correct this if necessary.
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`

3
docs/index.rst
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@@ -94,8 +94,7 @@ Links
:caption: CPU Interfaces :caption: CPU Interfaces
cpuif/introduction cpuif/introduction
cpuif/apb3 cpuif/apb
cpuif/apb4
cpuif/axi4lite cpuif/axi4lite
cpuif/passthrough cpuif/passthrough
cpuif/internal_protocol cpuif/internal_protocol