Clean up cpuif data_width_bytes usage

src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv

@@ -16,7 +16,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 {%- if cpuif.data_width == 8 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
-                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
                 {%- endif %}
                 cpuif_wr_data <= {{cpuif.signal("pwdata")}};
             end

src/peakrdl_regblock/cpuif/apb4/__init__.py

@@ -10,10 +10,6 @@ class APB4_Cpuif(CpuifBase):
     def signal(self, name:str) -> str:
         return "s_apb." + name.upper()
 
-    @property
-    def data_width_bytes(self) -> int:
-        return self.data_width // 8
-
 
 class APB4_Cpuif_flattened(APB4_Cpuif):
     @property

src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv

@@ -17,7 +17,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 {%- if cpuif.data_width == 8 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
-                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
                 {%- endif %}
                 cpuif_wr_data <= {{cpuif.signal("pwdata")}};
                 for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin

src/peakrdl_regblock/cpuif/axi4lite/__init__.py

@@ -10,10 +10,6 @@ class AXI4Lite_Cpuif(CpuifBase):
     def signal(self, name:str) -> str:
         return "s_axil." + name.upper()
 
-    @property
-    def data_width_bytes(self) -> int:
-        return self.data_width // 8
-
     @property
     def regblock_latency(self) -> int:
         return max(self.exp.min_read_latency, self.exp.min_write_latency)
@@ -49,7 +45,7 @@ class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
             "output logic " + self.signal("wready"),
             "input wire " + self.signal("wvalid"),
             f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
-            f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
+            f"input wire [{self.data_width_bytes-1}:0]" + self.signal("wstrb"),
 
             "input wire " + self.signal("bready"),
             "output logic " + self.signal("bvalid"),

src/peakrdl_regblock/cpuif/base.py

@@ -21,6 +21,10 @@ class CpuifBase:
         self.data_width = data_width
         self.addr_width = addr_width
 
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
     @property
     def port_declaration(self) -> str:
         raise NotImplementedError()