fill in more hwif utility functions for dereferencer

peakrdl/regblock/exporter.py

@@ -1,17 +1,18 @@
 import os
-from typing import TYPE_CHECKING
+from typing import Union
 
 import jinja2 as jj
-from systemrdl.node import Node, RootNode
+from systemrdl.node import AddrmapNode, RootNode
 
 from .addr_decode import AddressDecode
 from .field_logic import FieldLogic
 from .dereferencer import Dereferencer
 from .readback_mux import ReadbackMux
-from .signals import InferredSignal
+from .signals import InferredSignal, SignalBase
 
 from .cpuif.apb4 import APB4_Cpuif
 from .hwif import Hwif
+from .utils import get_always_ff_event
 
 class RegblockExporter:
     def __init__(self, **kwargs):
@@ -21,6 +22,16 @@ class RegblockExporter:
         if kwargs:
             raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
 
+
+        self.top_node = None # type: AddrmapNode
+        self.hwif = None # type: Hwif
+        self.address_decode = AddressDecode(self)
+        self.field_logic = FieldLogic(self)
+        self.readback_mux = ReadbackMux(self)
+        self.dereferencer = Dereferencer(self)
+        self.default_resetsignal = InferredSignal("rst")
+
+
         if user_template_dir:
             loader = jj.ChoiceLoader([
                 jj.FileSystemLoader(user_template_dir),
@@ -44,14 +55,17 @@ class RegblockExporter:
         )
 
 
-    def export(self, node:Node, output_path:str, **kwargs):
+    def export(self, node: Union[RootNode, AddrmapNode], output_path:str, **kwargs):
         # If it is the root node, skip to top addrmap
         if isinstance(node, RootNode):
-            node = node.top
+            self.top_node = node.top
+        else:
+            self.top_node = node
+
 
         cpuif_cls = kwargs.pop("cpuif_cls", APB4_Cpuif)
         hwif_cls = kwargs.pop("hwif_cls", Hwif)
-        module_name = kwargs.pop("module_name", node.inst_name)
+        module_name = kwargs.pop("module_name", self.top_node.inst_name)
         package_name = kwargs.pop("package_name", module_name + "_pkg")
 
         # Check for stray kwargs
@@ -63,8 +77,8 @@ class RegblockExporter:
         # TODO: Scan design...
 
         # TODO: derive this from somewhere
-        cpuif_reset = InferredSignal("rst")
-        reset_signals = [cpuif_reset]
+        cpuif_reset = self.default_resetsignal
+        reset_signals = set([cpuif_reset, self.default_resetsignal])
 
         cpuif = cpuif_cls(
             self,
@@ -73,17 +87,11 @@ class RegblockExporter:
             addr_width=32 # TODO:
         )
 
-        hwif = hwif_cls(
+        self.hwif = hwif_cls(
             self,
-            top_node=node,
             package_name=package_name,
         )
 
-        address_decode = AddressDecode(self, node)
-        field_logic = FieldLogic(self, node)
-        readback_mux = ReadbackMux(self, node)
-        dereferencer = Dereferencer(self, node, hwif, address_decode, field_logic)
-
         # Build Jinja template context
         context = {
             "module_name": module_name,
@@ -94,10 +102,11 @@ class RegblockExporter:
             "user_signals": [], # TODO:
             "interrupts": [], # TODO:
             "cpuif": cpuif,
-            "hwif": hwif,
-            "address_decode": address_decode,
-            "field_logic": field_logic,
-            "readback_mux": readback_mux,
+            "hwif": self.hwif,
+            "address_decode": self.address_decode,
+            "field_logic": self.field_logic,
+            "readback_mux": self.readback_mux,
+            "get_always_ff_event": get_always_ff_event,
         }
 
         # Write out design