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bslathi19/PeakRDL-regblock
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215 Commits 1 Branch 0 Tags
c95c332bd0134f6f209d9eb6233347a0648a9f38
Commit Graph

8 Commits

Author SHA1 Message Date
Alex Mykyta
833c515cd2 Re-enable xsim for testcases. Works better in Vivado 2024.2 2025-04-11 22:19:19 -07:00
Alex Mykyta
11d9f65dff Fix incorrect bit-order in packed struct output of external registers. #111 2024-12-18 21:17:31 -08:00
Alex Mykyta
b5b1ba790e Simulator compatibility updates 2023-10-22 20:43:34 -07:00
Alex Mykyta
d689bb7077 Reorganize how tb infrstructure selects toolchains 2023-10-22 11:04:43 -07:00
Alex Mykyta
ca9185dac7 Add support for external components. (#4 & #36) 2023-05-11 21:52:26 -07:00
Alex Mykyta
808067fac9 Fix synthesizability of fields with msb0 ordering 2022-10-17 23:24:35 -07:00
Alex Mykyta
03d77ea37b Add workaround to AXI4-Lite cpuif template to avoif quirk in Vivado xsim handling of non-power-of-2 array indexing. #7 2022-05-02 20:51:31 -07:00
Alex Mykyta
54d783e1ab Reorganize test dir to ensure test of installed pkg 2022-02-28 23:08:41 -08:00
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