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blathi/taxi_apb

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• cf30e28507 Add taxi apb blathi/taxi_apb Byron Lathi 2026-02-04 07:47:35 -08:00
• 9fc95b8769 Refactor readback mux implementation. Improves performance (#155) and eliminates illegal streaming operator usage (#165) Alex Mykyta 2025-12-10 23:17:33 -08:00
• 4201ce975e Fix OBI address truncation template for 1-byte datawidth case. #176 Alex Mykyta 2025-11-18 22:45:30 -08:00
• 61bffb7b91 Fix incorrect traversal into externals for read/write buffered regs. #167 Alex Mykyta 2025-11-16 20:27:57 -08:00
• efbddccc54 fix: handle error response for overlapped registers with read-only and write-only attributes (#178) Sebastien Baillou 2025-11-16 00:43:45 +01:00
• e1d7b3aa38 test: revert test_parity assign/deassign syntax with Xilinx simulator Sebastien Baillou 2025-11-16 00:38:10 +01:00
• 6597f889fa Improved the naming of tests which use the 'get_permutations' function. Adds the parameter values to the end of the test class. Benjamin Davis 2025-11-15 18:49:28 -07:00
• 75a2163f6d doc updates Alex Mykyta 2025-11-15 14:47:16 -08:00
• 7f572e05a4 Remove dangerous usage of non-public parts of the systemrdl-compiler API Alex Mykyta 2025-11-15 12:23:39 -08:00
• 610351d169 Fixed VSIM-7061 error in test_parity when using latest Questa Simulator. (#182) Benjamin Davis 2025-11-13 22:26:18 -07:00
• 3d5f9d8efb Added the ability to specify a regex filter for the part-name on the synthesis tests. Implemented as --synth-part. Closes #179 (#180) Benjamin Davis 2025-11-13 21:09:03 -07:00
• 543bf2be9a Remove dangerous usage of non-public parts of the systemrdl-compiler API Alex Mykyta 2025-11-04 23:05:50 -08:00
• 17465e5f97 version Alex Mykyta 2025-11-04 21:37:33 -08:00
• fcf4bffeb7 add missing docs Alex Mykyta 2025-11-04 21:28:51 -08:00
• ef2a18c8c0 Fix missing address truncation in OBI. #173 Alex Mykyta 2025-11-04 21:21:53 -08:00
• 529c4df98c Move port list generation out of Jinja template. #125, #153 Alex Mykyta 2025-10-25 19:38:00 -07:00
• 1926aff7b1 Add missing comment for external components Alex Mykyta 2025-10-25 19:23:28 -07:00
• d69af23be5 Error response for unmapped address or forbidden read/write access (#168) sbaillou 2025-10-26 02:22:15 +01:00
• bb765e6ae3 Add 's_' prefix to OBI port for consistency with all other cpuifs Alex Mykyta 2025-10-25 17:24:57 -07:00
• dafd693a1d OBI: Add testcase support. #157 Alex Mykyta 2025-10-24 19:36:36 -07:00
• f782c656ca OBI: Fix missing intf definition. Adjust coding style. #157 Alex Mykyta 2025-10-13 23:32:18 -07:00
• aa9a21046d feat: Add support for OBI protocol (#158) Daniel Keller 2025-09-22 16:54:27 +02:00
• 18cf2aabc7 don't emit write/read-buffer logic for external components Dana Sorensen 2025-10-23 20:37:27 -06:00
• 087b1f8611 added failing tests for external write/read-buffered components Dana Sorensen 2025-10-23 20:16:22 -06:00
• b097062e85 bump py versions Alex Mykyta 2025-10-13 22:42:40 -07:00
• a440cc1976 Add Xcelium simulator option Sebastien Baillou 2025-10-09 22:46:47 +02:00
• 08c24d4784 Switch to LGPLv3 license Alex Mykyta 2025-06-18 18:45:35 -07:00
• 0ff68fade9 Add more doc notes regarding packed structs Alex Mykyta 2025-09-19 10:30:15 -07:00
• c1af43b0cc Revise dependency constraints to use compatible versioning Alex Mykyta 2025-09-16 22:29:21 -07:00
• 4c819b4bcb fix doc phrasing Alex Mykyta 2025-08-08 17:05:58 -07:00
• 17ceaa7c01 version Alex Mykyta 2025-07-16 10:53:20 -07:00
• c95c332bd0 Fix xsim errors for fixedpoint testcase Alex Mykyta 2025-07-16 10:17:11 -07:00
• 588e1fee66 Add names to assertions. #151 Alex Mykyta 2025-07-16 10:12:46 -07:00
• e96537fd5c Fix incorrect NBA in Avalon always_comb template. #152 Alex Mykyta 2025-07-16 08:10:39 -07:00
• a917164642 Tidy up whitespace in generated package. #148 Alex Mykyta 2025-07-01 16:56:41 -07:00
• 105abdcba2 Update internal_protocol.rst (#145) Caio Alonso da Costa 2025-06-06 23:16:02 +02:00
• 8c0e772e0d Switch docs theme Alex Mykyta 2025-05-19 10:10:35 -07:00
• 9a0f6772d1 Update version Alex Mykyta 2025-05-15 22:14:39 -07:00
• d2b4911d5f Add signed/fixedpoint properties (#140) Dana Sorensen 2025-05-15 09:48:44 -06:00
• 62f66fb7ff Add xref to VHDL fork Alex Mykyta 2025-05-02 11:07:10 -07:00
• 8216a9f2f3 Fix classifier Alex Mykyta 2025-04-11 22:30:22 -07:00
• 833c515cd2 Re-enable xsim for testcases. Works better in Vivado 2024.2 Alex Mykyta 2025-04-11 22:19:19 -07:00
• 06bd567750 Increment version Alex Mykyta 2025-04-11 21:26:27 -07:00
• c3080d63ce Add version_info tuple Alex Mykyta 2025-04-11 21:19:35 -07:00
• b95ba354c3 Add simulation-time width assertions to SV interfaces. #128 Alex Mykyta 2025-04-11 21:14:15 -07:00
• 48ae215eda Add user parameters to regblock package. #112 Alex Mykyta 2025-04-10 22:16:13 -07:00
• 0a9a3ad51e Allow for write enable and sticky property Maciej Dudek 2024-04-10 02:14:11 +02:00
• a7cea87d40 Remove unreachable code Maciej Dudek 2024-04-09 23:14:17 +02:00
• 4aed443c55 Make swmod respect cpuif byte strobes. #137 Alex Mykyta 2025-04-10 21:26:08 -07:00
• bb2fead71a Add FAQ to docs Alex Mykyta 2025-03-08 18:35:46 -08:00
• 49e3311b85 cleanup text Alex Mykyta 2025-03-07 22:43:25 -08:00
• 3ed2e1f891 Simplify stickybit implementation for single-bit fields to not create redundant expression. #127 Alex Mykyta 2025-03-07 19:39:57 -08:00
• 6430dd4914 Emit error if field that is asynchronously reset uses a dynamic reset value. #129 Alex Mykyta 2025-03-07 19:20:44 -08:00
• d3cd51f500 Fix missing error message if multiple unconditional field assignments are inferred. #93 Alex Mykyta 2025-03-06 22:12:26 -08:00
• 54ac56e1c3 Add testcases to cover design validation errors Alex Mykyta 2025-03-06 22:10:05 -08:00
• f882e155d1 remove dead-code Alex Mykyta 2025-03-06 22:08:47 -08:00
• c53b11cf28 Add more specificity to stickybit conditional class Alex Mykyta 2025-03-06 21:24:49 -08:00
• 40687abd6b Type hinting cleanup Alex Mykyta 2025-03-03 21:36:57 -08:00
• 0258cac186 drop py3.6. Misc housekeeping Alex Mykyta 2025-01-04 23:23:15 -08:00
• 28ed82129f Add Addressmap block size to generated package (#134) Aylon Chaim Porat 2025-03-04 00:16:25 -05:00
• aba2af17af Increment version Alex Mykyta 2024-12-19 21:53:12 -08:00
• 8d82eb29d9 Add width cast to address decode loop iterators. #92 Alex Mykyta 2024-12-19 21:49:23 -08:00
• e788e7cafd Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be set to values beyond their saturation point if loaded through non-increment/decrement mechanism. #114 Alex Mykyta 2024-12-19 21:41:20 -08:00
• a15178c719 Use clog2 helper function to improve clarity. #116 Alex Mykyta 2024-12-19 19:47:41 -08:00
• 80a46a082b Fix incorrect address width calculation for external blocks. #116 Alex Mykyta 2024-12-19 19:40:57 -08:00
• 5f9d7308c2 Add next_q storage element to reset clause to avoid synthesis issues with async resets. #113 Alex Mykyta 2024-12-19 19:30:30 -08:00
• ebd82dde1b Add peakrdl-cli optional dependency Alex Mykyta 2024-12-19 19:04:48 -08:00
• 809195a72a install mising test package Alex Mykyta 2024-12-18 22:21:35 -08:00
• 1d7d47f49c More type hint workarounds Alex Mykyta 2024-12-18 22:20:35 -08:00
• 5c1bc35799 Type hint workarounds Alex Mykyta 2024-12-18 22:13:42 -08:00
• e0295ae526 Fixup test bitswap. mypy Alex Mykyta 2024-12-18 22:04:12 -08:00
• 11d9f65dff Fix incorrect bit-order in packed struct output of external registers. #111 Alex Mykyta 2024-12-18 21:17:31 -08:00
• 399f942201 Fix doc typos Alex Mykyta 2024-12-18 20:29:17 -08:00
• faa57c93b9 Add preprocessor ifndef around RTL assertions to allow exclusion. #104 Alex Mykyta 2024-12-17 22:31:30 -08:00
• ceb1f9b0c1 Add contributing guidelines, issue templates, and PR template Alex Mykyta 2024-05-04 18:04:52 -07:00
• a076609dad version Alex Mykyta 2024-03-31 22:21:54 -07:00
• 4dfd9b10d6 Add support for CPUIFs to have parameters #80 Alex Mykyta 2024-03-29 22:39:45 -07:00
• f25ba60bfc Add packed struct overlay for external register bitfields. #84 Alex Mykyta 2024-03-29 22:16:05 -07:00
• 840b54c6e1 Use explicit logic type for user enum declarations. #91 Alex Mykyta 2024-03-29 21:22:34 -07:00
• 653d4efc73 version Alex Mykyta 2024-03-20 20:02:40 -07:00
• 555efdfcc0 Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87 Alex Mykyta 2024-03-20 19:57:50 -07:00
• cf2be63c20 read_buffering & write_buffering: get_trigger's accesswidth and regwidth should be taken from trigger when trigger is of RegNode type, not from node Aylon Chaim Porat 2024-03-20 17:37:52 -04:00
• be8d84bba0 fix: a typo in SV template motchy 2024-03-10 23:44:29 +09:00
• 0d39774d22 Fixup whitespace Alex Mykyta 2024-01-05 20:51:19 -08:00
• 6a550abc69 Fix accidental blocking assignment in always_ff for read buffering storage elements Alex Mykyta 2024-01-05 19:57:47 -08:00
• 6433cd1fc8 Fix typo in pyproject keywords Alex Mykyta 2023-11-07 20:57:49 -08:00
• 45999555cf Update to use trusted deploy Alex Mykyta 2023-10-28 21:25:58 -07:00
• 2fedef64aa Add validation check for write buffered registers that trigger off of their own field. #39 Alex Mykyta 2023-10-25 21:54:01 -07:00
• f2cb2425b3 Migrate to pyproject.toml Alex Mykyta 2023-10-24 23:01:30 -07:00
• 62518b318b Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71 Alex Mykyta 2023-10-24 22:50:41 -07:00
• b5b1ba790e Simulator compatibility updates Alex Mykyta 2023-10-22 20:43:34 -07:00
• d689bb7077 Reorganize how tb infrstructure selects toolchains Alex Mykyta 2023-10-22 11:04:43 -07:00
• 683fc4d0ac Update version Alex Mykyta 2023-10-11 22:04:34 -07:00
• 1488b2c0ff Add missing doc req Alex Mykyta 2023-10-11 22:00:22 -07:00
• 0da6efe85c Fix hwif type name generation to properly handle parameterized component names. #70 Alex Mykyta 2023-10-11 21:58:10 -07:00
• c0e341579c fix typo Alex Mykyta 2023-09-29 05:55:54 -07:00
• 4fad6546fd docs yaml Alex Mykyta 2023-09-28 23:21:11 -07:00
• 333853b925 Fix axi4-lite write strobe width. #68 Alex Mykyta 2023-09-28 21:18:11 -07:00
• 639cafc28b Fix always_ff generation for non-reset fields and async default reset. #63 Alex Mykyta 2023-09-07 23:36:47 -07:00
• 7bb6c0c41a Fix xsim compatibility quirk Alex Mykyta 2023-09-07 23:16:58 -07:00