094648d1bbc9441554acf32347f7136a760290f5
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
56.8%
SystemVerilog
42.8%
Tcl
0.3%
Shell
0.1%