0d39774d227185a662a90db6c11f71ad162129f1
Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
56.8%
SystemVerilog
42.8%
Tcl
0.3%
Shell
0.1%