78 lines
2.7 KiB
Python
78 lines
2.7 KiB
Python
from typing import TYPE_CHECKING, Union
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from systemrdl.node import Node, FieldNode, SignalNode, RegNode
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from systemrdl.rdltypes import PropertyReference
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if TYPE_CHECKING:
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from .exporter import RegblockExporter
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from .hwif.base import HwifBase
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from .field_logic import FieldLogic
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class Dereferencer:
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"""
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This class provides an interface to convert conceptual SystemRDL references
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into Verilog identifiers
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"""
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def __init__(self, exporter:'RegblockExporter', hwif:'HwifBase', field_logic: "FieldLogic", top_node:Node):
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self.exporter = exporter
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self.hwif = hwif
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self.field_logic = field_logic
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self.top_node = top_node
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def get_value(self, obj: Union[int, FieldNode, SignalNode, PropertyReference]) -> str:
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"""
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Returns the Verilog string that represents the value associated with the object.
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If given a simple scalar value, then the corresponding Verilog literal is returned.
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If obj references a structural systemrdl object, then the corresponding Verilog
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expression is returned that represents its value.
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"""
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if isinstance(obj, int):
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# Is a simple scalar value
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return f"'h{obj:x}"
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elif isinstance(obj, FieldNode):
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if obj.implements_storage:
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return self.field_logic.get_storage_identifier(obj)
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if self.hwif.has_value_input(obj):
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return self.hwif.get_input_identifier(obj)
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# Field does not have a storage element, nor does it have a HW input
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# must be a constant value as defined by its reset value
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reset_value = obj.get_property('reset')
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if reset_value is not None:
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return f"'h{reset_value:x}"
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else:
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# No reset value defined!
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# Fall back to a value of 0
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return "'h0"
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elif isinstance(obj, SignalNode):
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# Signals are always inputs from the hwif
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return self.hwif.get_input_identifier(obj)
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elif isinstance(obj, PropertyReference):
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# TODO: Table G1 describes other possible ref targets
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# Value reduction properties
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val = self.get_value(obj.node)
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if obj.name == "anded":
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return f"&({val})"
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elif obj.name == "ored":
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return f"|({val})"
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elif obj.name == "xored":
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return f"^({val})"
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else:
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raise RuntimeError
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else:
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raise RuntimeError
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def get_access_strobe(self, reg: RegNode) -> str:
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"""
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Returns the Verilog string that represents the register's access strobe
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"""
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# TODO: Implement me
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raise NotImplementedError
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