16bfab62e905620afe70894c902b5c96f8e87b01
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
56.8%
SystemVerilog
42.8%
Tcl
0.3%
Shell
0.1%