139 lines
4.7 KiB
Python
139 lines
4.7 KiB
Python
from typing import TYPE_CHECKING, Union, List
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from systemrdl.node import AddrmapNode, AddressableNode, RegNode, FieldNode
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from .utils import get_indexed_path
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from .struct_generator import RDLStructGenerator
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from .forloop_generator import RDLForLoopGenerator
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from .identifier_filter import kw_filter as kwf
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if TYPE_CHECKING:
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from .exporter import RegblockExporter
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class AddressDecode:
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def __init__(self, exp:'RegblockExporter'):
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self.exp = exp
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@property
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def top_node(self) -> AddrmapNode:
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return self.exp.top_node
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def get_strobe_struct(self) -> str:
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struct_gen = DecodeStructGenerator()
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s = struct_gen.get_struct(self.top_node, "decoded_reg_strb_t")
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assert s is not None # guaranteed to have at least one reg
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return s
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def get_implementation(self) -> str:
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gen = DecodeLogicGenerator(self)
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s = gen.get_content(self.top_node)
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assert s is not None
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return s
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def get_access_strobe(self, node: Union[RegNode, FieldNode], reduce_substrobes: bool=True) -> str:
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"""
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Returns the Verilog string that represents the register/field's access strobe.
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"""
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if isinstance(node, FieldNode):
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field = node
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path = get_indexed_path(self.top_node, node.parent)
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regwidth = node.parent.get_property('regwidth')
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accesswidth = node.parent.get_property('accesswidth')
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if regwidth > accesswidth:
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# Is wide register.
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# Determine the substrobe(s) relevant to this field
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sidx_hi = field.msb // accesswidth
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sidx_lo = field.lsb // accesswidth
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if sidx_hi == sidx_lo:
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suffix = f"[{sidx_lo}]"
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else:
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suffix = f"[{sidx_hi}:{sidx_lo}]"
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path += suffix
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if sidx_hi != sidx_lo and reduce_substrobes:
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return "|decoded_reg_strb." + path
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else:
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path = get_indexed_path(self.top_node, node)
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return "decoded_reg_strb." + path
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class DecodeStructGenerator(RDLStructGenerator):
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def enter_Reg(self, node: 'RegNode') -> None:
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# if register is "wide", expand the strobe to be able to access the sub-words
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n_subwords = node.get_property("regwidth") // node.get_property("accesswidth")
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self.add_member(
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kwf(node.inst_name),
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width=n_subwords,
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array_dimensions=node.array_dimensions,
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)
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# Stub out
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def exit_Reg(self, node: 'RegNode') -> None:
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pass
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def enter_Field(self, node: 'FieldNode') -> None:
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pass
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class DecodeLogicGenerator(RDLForLoopGenerator):
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def __init__(self, addr_decode: AddressDecode) -> None:
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self.addr_decode = addr_decode
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super().__init__()
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# List of address strides for each dimension
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self._array_stride_stack = [] # type: List[List[int]]
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def enter_AddressableComponent(self, node: 'AddressableNode') -> None:
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super().enter_AddressableComponent(node)
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if not node.is_array:
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return
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# Collect strides for each array dimension
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current_stride = node.array_stride
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strides = []
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for dim in reversed(node.array_dimensions):
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strides.append(current_stride)
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current_stride *= dim
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strides.reverse()
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self._array_stride_stack.extend(strides)
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def _get_address_str(self, node:AddressableNode, subword_offset: int=0) -> str:
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a = f"'h{(node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address + subword_offset):x}"
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for i, stride in enumerate(self._array_stride_stack):
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a += f" + i{i}*'h{stride:x}"
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return a
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def enter_Reg(self, node: RegNode) -> None:
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regwidth = node.get_property('regwidth')
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accesswidth = node.get_property('accesswidth')
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if regwidth == accesswidth:
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s = f"{self.addr_decode.get_access_strobe(node)} = cpuif_req_masked & (cpuif_addr == {self._get_address_str(node)});"
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self.add_content(s)
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else:
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# Register is wide. Create a substrobe for each subword
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n_subwords = regwidth // accesswidth
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subword_stride = accesswidth // 8
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for i in range(n_subwords):
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s = f"{self.addr_decode.get_access_strobe(node)}[{i}] = cpuif_req_masked & (cpuif_addr == {self._get_address_str(node, subword_offset=(i*subword_stride))});"
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self.add_content(s)
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def exit_AddressableComponent(self, node: 'AddressableNode') -> None:
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super().exit_AddressableComponent(node)
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if not node.is_array:
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return
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for _ in node.array_dimensions:
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self._array_stride_stack.pop()
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