4201ce975eef896e2314b88ce3b595034b118f18
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
56.8%
SystemVerilog
42.8%
Tcl
0.3%
Shell
0.1%