81 lines
2.2 KiB
Markdown
81 lines
2.2 KiB
Markdown
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# Test Dependencies
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## ModelSim
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Testcases require an installation of ModelSim/QuestaSim, and for `vlog` & `vsim`
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commands to be visible via the PATH environment variable.
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ModelSim - Intel FPGA Edition can be downloaded for free from https://fpgasoftware.intel.com/ and is sufficient to run unit tests.
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## Python Packages
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Install dependencies required for running tests
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```bash
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python3 -m pip install test/requirements.txt
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```
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# Running tests
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Tests can be launched from the test directory using `pytest``.
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Use ``pytest -n auto`` to run tests in parallel.
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To run all tests:
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```bash
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cd test/
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pytest
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```
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You can also run a specific testcase. For example:
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```bash
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cd test/test_hw_access
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pytest
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```
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# Test organization
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The goal for this test infrastructre is to make it easy to add small-standalone
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testcases, with minimal repetition/boilerplate code that is usually present in
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SystemVerilog testbenches.
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To accomplish this, Jinja templates are used extensively to generate the
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resulting ``tb.sv`` file, as well as assist in dynamic testcase parameterization.
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## CPU Interfaces
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Each CPU interface type is described in its own folder as follows:
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`lib/cpuifs/<type>/__init__.py`
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: Definitions for CPU Interface test mode classes.
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`lib/cpuifs/<type>/tb_inst.sv`
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: Jinja template that defines how the CPU interface is declared & instantiated in the testbench file.
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`lib/cpuifs/<type>/*.sv`
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: Any other files required for compilation.
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## Testcase
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Each testcase group has its own folder and contains the following:
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`test_*/__init__.py`
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: Empty file required for test discovery.
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`test_*/regblock.rdl`
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: Testcase RDL file. Testcase infrastructure will automatically compile this and generate the regblock output SystemVerilog.
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`test_*/tb_template.sv`
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: Jinja template that defines the testcase-specific sequence.
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`test_*/testcase.py`
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: Defines Python unittest testcase entry point.
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## Parameterization
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Testcase classes can be parameterized using the [parameterized](https://github.com/wolever/parameterized) extension. This allows the same testcase to be run against multiple permutations of regblock export modes such as CPU interfaces, retiming flop stages, or even RDL parameterizations.
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