147 lines
6.1 KiB
Python
147 lines
6.1 KiB
Python
from typing import TYPE_CHECKING, Set, List
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from collections import OrderedDict
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from systemrdl.walker import RDLListener, RDLWalker
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from systemrdl.node import SignalNode, AddressableNode
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if TYPE_CHECKING:
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from systemrdl.node import Node, RegNode, FieldNode
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from .exporter import RegblockExporter
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class DesignScanner(RDLListener):
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"""
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Scans through the register model and validates that any unsupported features
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are not present.
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Also collects any information that is required prior to the start of the export process.
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"""
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def __init__(self, exp:'RegblockExporter') -> None:
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self.exp = exp
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self.cpuif_data_width = 0
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self.msg = exp.top_node.env.msg
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# Keep track of max regwidth encountered in a given block
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self.max_regwidth_stack = [] # type: List[int]
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# Collections of signals that were actually referenced by the design
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self.in_hier_signal_paths = set() # type: Set[str]
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self.out_of_hier_signals = OrderedDict() # type: OrderedDict[str, SignalNode]
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def _get_out_of_hier_field_reset(self) -> None:
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current_node = self.exp.top_node.parent
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while current_node is not None:
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for signal in current_node.signals():
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if signal.get_property('field_reset'):
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path = signal.get_path()
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self.out_of_hier_signals[path] = signal
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return
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current_node = current_node.parent
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def do_scan(self) -> None:
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# Collect cpuif reset, if any.
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cpuif_reset = self.exp.top_node.cpuif_reset
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if cpuif_reset is not None:
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path = cpuif_reset.get_path()
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rel_path = cpuif_reset.get_rel_path(self.exp.top_node)
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if rel_path.startswith("^"):
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self.out_of_hier_signals[path] = cpuif_reset
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else:
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self.in_hier_signal_paths.add(path)
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# collect out-of-hier field_reset, if any
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self._get_out_of_hier_field_reset()
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# Ensure addrmap is not a bridge. This concept does not make sense for
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# terminal components.
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if self.exp.top_node.get_property('bridge'):
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self.msg.error(
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"Regblock generator does not support exporting bridge address maps",
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self.exp.top_node.inst.property_src_ref.get('bridge', self.exp.top_node.inst.inst_src_ref)
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)
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RDLWalker().walk(self.exp.top_node, self)
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if self.msg.had_error:
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self.msg.fatal(
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"Unable to export due to previous errors"
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)
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raise ValueError
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def enter_Reg(self, node: 'RegNode') -> None:
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regwidth = node.get_property('regwidth')
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self.max_regwidth_stack[-1] = max(self.max_regwidth_stack[-1], regwidth)
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# The CPUIF's bus width is sized according to the largest register in the design
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# TODO: make this user-overridable once more flexible regwidth/accesswidths are supported
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self.cpuif_data_width = max(self.cpuif_data_width, regwidth)
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# TODO: remove this limitation eventually
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if regwidth != self.cpuif_data_width:
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self.msg.error(
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"register blocks with non-uniform regwidths are not supported yet",
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node.inst.property_src_ref.get('regwidth', node.inst.inst_src_ref)
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)
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# TODO: remove this limitation eventually
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if regwidth != node.get_property('accesswidth'):
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self.msg.error(
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"Registers that have an accesswidth different from the register width are not supported yet",
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node.inst.property_src_ref.get('accesswidth', node.inst.inst_src_ref)
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)
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def enter_AddressableComponent(self, node: AddressableNode) -> None:
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self.max_regwidth_stack.append(0)
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def exit_AddressableComponent(self, node: AddressableNode) -> None:
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max_block_regwidth = self.max_regwidth_stack.pop()
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if self.max_regwidth_stack:
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self.max_regwidth_stack[-1] = max(self.max_regwidth_stack[-1], max_block_regwidth)
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alignment = int(max_block_regwidth / 8)
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if (node.raw_address_offset % alignment) != 0:
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self.msg.error(
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f"Unaligned registers are not supported. Address offset of instance '{node.inst_name}' must be a multiple of {alignment}",
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node.inst.inst_src_ref
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)
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if node.is_array and (node.array_stride % alignment) != 0:
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self.msg.error(
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f"Unaligned registers are not supported. Address stride of instance array '{node.inst_name}' must be a multiple of {alignment}",
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node.inst.inst_src_ref
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)
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def enter_Component(self, node: 'Node') -> None:
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if node.external and (node != self.exp.top_node):
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self.msg.error(
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"Exporter does not support external components",
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node.inst.inst_src_ref
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)
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def enter_Signal(self, node: 'SignalNode') -> None:
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# If encountering a CPUIF reset that is nested within the register model,
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# warn that it will be ignored.
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# Only cpuif resets in the top-level node or above will be honored
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if node.get_property('cpuif_reset') and (node.parent != self.exp.top_node):
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self.msg.warning(
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"Only cpuif_reset signals that are instantiated in the top-level "
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+ "addrmap or above will be honored. Any cpuif_reset signals nested "
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+ "within children of the addrmap being exported will be ignored.",
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node.inst.inst_src_ref
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)
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if node.get_property('field_reset'):
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path = node.get_path()
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self.in_hier_signal_paths.add(path)
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def enter_Field(self, node: 'FieldNode') -> None:
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for prop_name in node.list_properties():
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value = node.get_property(prop_name)
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if isinstance(value, SignalNode):
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path = value.get_path()
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rel_path = value.get_rel_path(self.exp.top_node)
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if rel_path.startswith("^"):
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self.out_of_hier_signals[path] = value
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else:
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self.in_hier_signal_paths.add(path)
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