bslathi19/PeakRDL-regblock

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Alex Mykyta 9e100492e4 Update actions

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2023-01-18 20:34:44 -08:00

Add option to override CPUIF address width. #25

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Add 'rd_swacc' and 'wr_swacc' UDPs. #21

2022-11-09 21:25:02 -08:00

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fix error msg phrasing

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Add 'rd_swacc' and 'wr_swacc' UDPs. #21

2022-11-09 21:25:02 -08:00

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Improve template path handling. Add synthesis tests

2022-02-23 22:53:54 -08:00

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Implement write buffering (#22 )

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README.md

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details