238 lines
8.1 KiB
Systemverilog
238 lines
8.1 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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// Enable all interrupts
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cpuif.write('h100, 'h1FF); // ctrl_enable
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cpuif.write('h104, 'h000); // ctrl_mask
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cpuif.write('h108, 'h1FF); // ctrl_haltenable
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cpuif.write('h10C, 'h000); // ctrl_haltmask
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//--------------------------------------------------------------------------
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// Test level_irqs_1
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cpuif.assert_read('h0, 'h000);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b0);
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cb.hwif_in.level_irqs_1.irq0.next <= 'h0F;
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@cb;
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cb.hwif_in.level_irqs_1.irq0.next <= 'h00;
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cpuif.assert_read('h0, 'h00F);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cpuif.write('h0, 'h3);
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cpuif.assert_read('h0, 'h00C);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cpuif.write('h0, 'hC);
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cpuif.assert_read('h0, 'h000);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b0);
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cb.hwif_in.level_irqs_1.irq1.next <= 'b1;
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@cb;
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cb.hwif_in.level_irqs_1.irq1.next <= 'b0;
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cpuif.assert_read('h0, 'h100);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cpuif.write('h0, 'h100);
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@cb;
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assert(cb.hwif_out.level_irqs_1.intr == 1'b0);
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cpuif.assert_read('h0, 'h0);
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cb.hwif_in.level_irqs_1.irq1.next <= 'b1;
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cpuif.assert_read('h0, 'h100);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cpuif.write('h0, 'h100);
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cpuif.assert_read('h0, 'h100);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cb.hwif_in.level_irqs_1.irq1.next <= 'b0;
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cpuif.assert_read('h0, 'h100);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b1);
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cpuif.write('h0, 'h100);
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cpuif.assert_read('h0, 'h000);
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assert(cb.hwif_out.level_irqs_1.intr == 1'b0);
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//--------------------------------------------------------------------------
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// Test level_irqs_2
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cpuif.assert_read('h4, 'h000);
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assert(cb.hwif_out.level_irqs_2.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b0);
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cb.hwif_in.level_irqs_2.irq0.next <= 'h0F;
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@cb;
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cb.hwif_in.level_irqs_2.irq0.next <= 'h00;
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cpuif.assert_read('h4, 'h00F);
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assert(cb.hwif_out.level_irqs_2.intr == 1'b1);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b1);
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cpuif.write('h100, 'h0); // ctrl_enable
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@cb;
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assert(cb.hwif_out.level_irqs_2.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b1);
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cpuif.write('h108, 'h0); // ctrl_haltenable
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@cb;
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assert(cb.hwif_out.level_irqs_2.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b0);
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cpuif.write('h100, 'h1FF); // ctrl_enable
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cpuif.write('h108, 'h1FF); // ctrl_haltenable
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@cb;
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assert(cb.hwif_out.level_irqs_2.intr == 1'b1);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b1);
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cpuif.write('h4, 'h1FF);
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@cb;
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assert(cb.hwif_out.level_irqs_2.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_2.halt == 1'b0);
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//--------------------------------------------------------------------------
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// Test level_irqs_3
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cpuif.assert_read('h8, 'h000);
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assert(cb.hwif_out.level_irqs_3.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_3.halt == 1'b0);
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cb.hwif_in.level_irqs_3.irq0.next <= 'h0F;
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@cb;
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cb.hwif_in.level_irqs_3.irq0.next <= 'h00;
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cpuif.assert_read('h8, 'h00F);
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assert(cb.hwif_out.level_irqs_3.intr == 1'b1);
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assert(cb.hwif_out.level_irqs_3.halt == 1'b1);
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cpuif.write('h104, 'h0F); // ctrl_mask
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@cb;
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assert(cb.hwif_out.level_irqs_3.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_3.halt == 1'b1);
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cpuif.write('h10C, 'hF); // ctrl_haltmask
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@cb;
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assert(cb.hwif_out.level_irqs_3.intr == 1'b0);
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assert(cb.hwif_out.level_irqs_3.halt == 1'b0);
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cpuif.write('h104, 'h0); // ctrl_mask
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cpuif.write('h10C, 'h0); // ctrl_haltmask
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@cb;
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assert(cb.hwif_out.level_irqs_3.intr == 1'b1);
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assert(cb.hwif_out.level_irqs_3.halt == 1'b1);
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//--------------------------------------------------------------------------
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// Test posedge_irqs
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cpuif.assert_read('h10, 'h000);
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assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
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cb.hwif_in.posedge_irqs.irq1.next <= 1'b1;
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@cb;
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cpuif.assert_read('h10, 'h100);
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assert(cb.hwif_out.posedge_irqs.intr == 1'b1);
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cpuif.write('h10, 'h100);
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cpuif.assert_read('h10, 'h000);
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assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
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cpuif.assert_read('h10, 'h000);
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cb.hwif_in.posedge_irqs.irq1.next <= 1'b0;
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cpuif.assert_read('h10, 'h000);
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assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
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//--------------------------------------------------------------------------
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// Test negedge_irqs
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cpuif.assert_read('h20, 'h000);
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assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
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cb.hwif_in.negedge_irqs.irq1.next <= 1'b1;
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@cb;
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cpuif.assert_read('h20, 'h000);
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assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
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cb.hwif_in.negedge_irqs.irq1.next <= 1'b0;
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cpuif.assert_read('h20, 'h100);
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assert(cb.hwif_out.negedge_irqs.intr == 1'b1);
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cpuif.write('h20, 'h100);
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cpuif.assert_read('h20, 'h000);
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assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
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cpuif.assert_read('h20, 'h000);
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//--------------------------------------------------------------------------
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// Test bothedge_irqs
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cpuif.assert_read('h30, 'h000);
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assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
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cb.hwif_in.bothedge_irqs.irq1.next <= 1'b1;
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cpuif.assert_read('h30, 'h100);
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assert(cb.hwif_out.bothedge_irqs.intr == 1'b1);
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cpuif.write('h30, 'h100);
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cpuif.assert_read('h30, 'h000);
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assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
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cpuif.assert_read('h30, 'h000);
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cb.hwif_in.bothedge_irqs.irq1.next <= 1'b0;
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cpuif.assert_read('h30, 'h100);
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assert(cb.hwif_out.bothedge_irqs.intr == 1'b1);
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cpuif.write('h30, 'h100);
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cpuif.assert_read('h30, 'h000);
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assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
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cpuif.assert_read('h30, 'h000);
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//--------------------------------------------------------------------------
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cpuif.assert_read('h40, 'h000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cb.hwif_in.level_irqs_1.irq0.next <= 'h01;
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@cb;
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cb.hwif_in.level_irqs_1.irq0.next <= 'h00;
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cpuif.assert_read('h40, 'b0001);
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assert(cb.hwif_out.top_irq.intr == 1'b1);
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cpuif.write('h0, 'h01);
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cpuif.assert_read('h40, 'b0000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cb.hwif_in.posedge_irqs.irq0.next <= 'h01;
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@cb;
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cb.hwif_in.posedge_irqs.irq0.next <= 'h00;
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cpuif.assert_read('h40, 'b0010);
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assert(cb.hwif_out.top_irq.intr == 1'b1);
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cpuif.write('h10, 'h01);
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cpuif.assert_read('h40, 'b0000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cb.hwif_in.negedge_irqs.irq0.next <= 'h01;
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@cb;
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cb.hwif_in.negedge_irqs.irq0.next <= 'h00;
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@cb;
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cpuif.assert_read('h40, 'b0100);
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assert(cb.hwif_out.top_irq.intr == 1'b1);
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cpuif.write('h20, 'h01);
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cpuif.assert_read('h40, 'b0000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cb.hwif_in.bothedge_irqs.irq0.next <= 'h01;
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@cb;
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cb.hwif_in.bothedge_irqs.irq0.next <= 'h00;
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cpuif.assert_read('h40, 'b1000);
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assert(cb.hwif_out.top_irq.intr == 1'b1);
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cpuif.write('h30, 'h01);
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cpuif.assert_read('h40, 'b0000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cpuif.write('h108, 'h000); // ctrl_haltenable
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cb.hwif_in.level_irqs_2.irq0.next <= 'h01;
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@cb;
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cb.hwif_in.level_irqs_2.irq0.next <= 'h00;
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@cb;
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cpuif.assert_read('h40, 'b00000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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cpuif.write('h108, 'h001); // ctrl_haltenable
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cpuif.assert_read('h40, 'b10000);
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assert(cb.hwif_out.top_irq.intr == 1'b1);
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cpuif.write('h4, 'h01);
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cpuif.assert_read('h40, 'b00000);
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assert(cb.hwif_out.top_irq.intr == 1'b0);
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//--------------------------------------------------------------------------
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// Test multi-bit sticky reg
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cpuif.assert_read('h50, 'h00);
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cb.hwif_in.stickyreg.stickyfield.next <= 'h12;
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@cb;
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cb.hwif_in.stickyreg.stickyfield.next <= 'h34;
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@cb;
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cb.hwif_in.stickyreg.stickyfield.next <= 'h56;
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@cb;
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cpuif.assert_read('h50, 'h12);
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cpuif.write('h50, 'h00);
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@cb;
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cb.hwif_in.stickyreg.stickyfield.next <= 'h78;
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@cb;
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cpuif.assert_read('h50, 'h56);
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{% endblock %}
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