bslathi19/PeakRDL-regblock
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Alex Mykyta a8bf3c5132 doc tweaks
2022-02-28 22:10:09 -08:00
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2022-02-28 22:10:09 -08:00
peakrdl/regblock
Add precedence test. fixup docs
2022-02-28 22:05:24 -08:00
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Add precedence test. fixup docs
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Improve template path handling. Add synthesis tests
2022-02-23 22:53:54 -08:00
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2021-06-01 21:57:12 -07:00
MANIFEST.in
Add counter support
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setup.py
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README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%