* declared intwidth, fracwidth, and is_signed UDPs * fix boolean type name in UDP definition * generate hwif fields with fixedpoint indices * make "counter" and "encode" properties mutualy exclusive with signed/fixedpoint * add signed/unsigned to hwif * improved fixedpoint error messages, added validation tests * added fixedpoint tests * fixedpoint/signed not allowed for signal components * added signed/fixedpoint UDP docs * handle single-bit fixedpoint numbers * fix too many positional arguments lint * changed spelling of fixedpoint to fixed-point * use "logic" in place of "unsigned logic" * split signed and fixedpoint docs, added examples * allow enums with is_signed=false * split signed and fixedpoint implementations * assorted nits picked * updated is_signed validation unit test
HDL Source Files
This folder contains some SystemVerilog definitions that are useful collateral to be used alongside this project.
These reference files are free to use for any purpose and are not covered by this project's GPLv3 license.
If for whatever reason you feel the need to reference a license when using these, then lets go with the MIT License