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Alex Mykyta c3bfc2d416 documentation
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peakrdl/regblock
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Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions
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README.md

Documentation Status PyPI - Python Version

IMPORTANT

This project has no official releases yet and is still under active development!

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
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Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%