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Alex Mykyta d3a8266c6d tweak readme
2022-05-02 21:01:16 -07:00
.github/workflows
Enable Vivado's xsim to run on some simpler testcases for better compile-check coverage. #7
2022-05-02 20:22:55 -07:00
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sentences are hard
2022-03-20 23:00:31 -07:00
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Improve template path handling. Add synthesis tests
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2021-06-01 21:57:12 -07:00
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Reorganize test dir to ensure test of installed pkg
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README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%