44 lines
1.5 KiB
ReStructuredText
44 lines
1.5 KiB
ReStructuredText
Known Issues & Limitations
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==========================
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Not all SystemRDL features are supported by this exporter. For a listing of
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supported properties, see the appropriate property listing page in the following
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sections.
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External Components
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-------------------
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Regfiles, registers & fields instantiated using the ``external`` keyword are not supported yet.
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Alias Registers
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---------------
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Registers instantiated using the ``alias`` keyword are not supported yet.
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Unaligned Registers
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-------------------
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All address offsets & strides shall be a multiple of the regwidth used. Specifically:
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* Each register's address and array stride shall be aligned to it's regwidth.
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* Each regfile or addrmap shall use an offset and stride that is a multiple of the largest regwidth it encloses.
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No partial writes
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-----------------
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Some protocols describe byte-level write strobes. These are not supported yet.
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All write transfers must access the entire register width.
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Register width, Access width and CPUIF bus width
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------------------------------------------------
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To keep the initial architecture simpler, currently ``regwidth``, ``accesswidth``
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and the resulting CPU bus width has some limitations:
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* All registers shall have ``regwidth`` == ``accesswidth``
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* ``regwidth`` shall be the same across all registers within the block being exported.
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* The CPU interface's bus width is statically determined by the ``regwidth`` used.
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I have plans to remove these restrictions and allow for more flexibility in the future.
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