e7e941d27b308a98b60ef6d0b04855e41afb10fc
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PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
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SystemVerilog
42.8%
Tcl
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Shell
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