ee8d74b4558246bd4ba4566d840562e178b361d3
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PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
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SystemVerilog
42.8%
Tcl
0.3%
Shell
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