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Alex Mykyta f70bdf774c testcase framework
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peakrdl/regblock
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fill in more hwif utility functions for dereferencer
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README.md

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Installing

(Not published to PyPi yet)

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Description
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Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%