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Enable Client Tag, remove ILA

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This commit is contained in:
Byron Lathi
2025-11-11 23:08:19 -08:00
parent df377dda5d
commit 13b238e51e
9 changed files with 297 additions and 6373 deletions
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3
ip/ila_0/.gitignore vendored
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@@ -1,3 +0,0 @@
*
!.gitignore
!*.xci

6304
ip/ila_0/ila_0.xci
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3
ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc Normal file
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@@ -0,0 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:4
eof:

7
ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr Normal file
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@@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>

236
ip/managed_ip_project/managed_ip_project.xpr Normal file
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@@ -0,0 +1,236 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="68" Path="/cluster/projects/alibaba_pcie_2/ip/managed_ip_project/managed_ip_project.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="105a1e72e2fb4b7296f713ba18ab6d9f"/>
<Option Name="Part" Val="xcku3p-ffvb676-2-e"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2024.2"/>
<Option Name="SimulatorVersionModelSim" Val="2024.1"/>
<Option Name="SimulatorVersionQuesta" Val="2024.1"/>
<Option Name="SimulatorVersionXcelium" Val="24.03.003"/>
<Option Name="SimulatorVersionVCS" Val="V-2023.12-SP1"/>
<Option Name="SimulatorVersionRiviera" Val="2024.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="None"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Managed_IP"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/../ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/../ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="UseInlineHdlIP" Val="TRUE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../pcie4_uscale_plus_0/pcie4_uscale_plus_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ila_0/ila_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ila_1/ila_1.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../ila_2/ila_2.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku3p-ffvb676-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku3p-ffvb676-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

4
ip/pcie4_uscale_plus_0/pcie4_uscale_plus_0.xci
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@@ -19,7 +19,7 @@
"AXISTEN_IF_EXT_512_RC_STRADDLE": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
"AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"AXISTEN_IF_RC_STRADDLE": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"axisten_if_enable_client_tag": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
"axisten_if_enable_client_tag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
"type1_membase_memlimit_enable": [ { "value": "Disabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"type1_prefetchable_membase_memlimit": [ { "value": "Disabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -983,7 +983,7 @@
"pcie_blk_locn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"PIPE_SIM": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"PHY_READY_RETRY": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"AXISTEN_IF_ENABLE_CLIENT_TAG": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"AXISTEN_IF_ENABLE_CLIENT_TAG": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
"PCIE_FAST_CONFIG": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
"EXT_STARTUP_PRIMITIVE": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"PL_INTERFACE": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],

1
sources.list
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@@ -1,5 +1,4 @@
ip/pcie4_uscale_plus_0/pcie4_uscale_plus_0.xci
ip/ila_0/ila_0.xci
src/alibaba_cloud.xdc
src/alibaba_pcie_top.sv
src/regs/verilator.vlt

26
src/pcie_dma_wrapper.sv
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@@ -103,32 +103,6 @@ always_comb begin
hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
end
`ifndef SIM
ila_0 rd_desc_ila (
.clk (clk),
.probe0 (rd_desc.req_src_addr),
.probe1 (rd_desc.req_dst_addr),
.probe2 (rd_desc.req_len),
.probe3 (rd_desc.req_tag),
.probe4 (rd_desc.req_valid),
.probe5 (rd_desc.req_ready),
.probe6 (rd_desc.sts_valid)
);
ila_0 wr_desc_ila (
.clk (clk),
.probe0 (wr_desc.req_dst_addr),
.probe1 (wr_desc.req_src_addr),
.probe2 (wr_desc.req_len),
.probe3 (wr_desc.req_tag),
.probe4 (wr_desc.req_valid),
.probe5 (wr_desc.req_ready),
.probe6 (wr_desc.sts_valid)
);
`endif
taxi_dma_if_pcie_us #(
// disable flow control, shouldn't be needed
.RD_TX_FC_EN('0),

86
sw/test/pcie_dma_test.c
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@@ -76,13 +76,15 @@ int virt_to_phys_user(uintptr_t *paddr, uintptr_t vaddr)
int main(void)
{
uint32_t dma_mem_addr = 0x10;
uint32_t dma_mem_addr = 0x00;
/* Instead of allocating source, just use the constant string */
//char* src_1 = "Hello, world! This is some data that is stored in system memory!";
char* src_1 = "AAAA";
//char* src_2 = "This is many different words, in a different order";
char* src_2 = "BBBB";
//printf("Allocating 1024 bytes as source\n");
//uintptr_t src = (uintptr_t)malloc(1024);
char* src = "Hello, world! This is some data that is stored in system memory!";
char* src = (char*)malloc(1024);
printf("Virtual address: %lx\n", src);
uintptr_t src_phys;
virt_to_phys_user(&src_phys, (uintptr_t)src);
@@ -98,7 +100,6 @@ int main(void)
printf("Physical address: %lx\n", dst_phys);
printf("\n\n");
memset((void*)dst, 0, 1024);
printf("mmaping PCIe space\n");
// this is hardcoded, seems to be deterministic.
@@ -107,38 +108,49 @@ int main(void)
uint32_t* pcie_base = (uint32_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
printf("Virtual PCIe Base: %p\n", pcie_base);
printf("Sending read DMA\n");
pcie_base[0] = (uint32_t)src_phys;
pcie_base[1] = (uint32_t)(src_phys >> 32);
pcie_base[2] = dma_mem_addr;
pcie_base[3] = strlen(src);
for (int i = 0; i < 4; i++) {
printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
for (int i = 0; i < 2; i++) {
if (i == 0) {
strncpy((void*)src, src_1, 1024);
} else {
strncpy((void*)src, src_2, 1024);
}
memset((void*)dst, 0, 1024);
printf("Sending read DMA\n");
pcie_base[0] = (uint32_t)src_phys;
pcie_base[1] = (uint32_t)(src_phys >> 32);
pcie_base[2] = dma_mem_addr;
pcie_base[3] = strlen(src);
for (int i = 0; i < 4; i++) {
printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
}
pcie_base[4] = 1;
printf("%d\n", pcie_base[4]);
printf("\n\n");
printf("Sending write DMA\n");
printf("Sending read DMA\n");
pcie_base[8] = (uint32_t)dst_phys;
pcie_base[9] = (uint32_t)(dst_phys >> 32);
pcie_base[10] = dma_mem_addr;
pcie_base[11] = strlen(src);
for (int i = 8; i < 12; i++) {
printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
}
pcie_base[12] = 1;
printf("%d\n", pcie_base[12]);
printf("\n\n");
printf("strlen(dst)=%d\n", strlen(dst));
printf("%s\n", dst);
}
pcie_base[4] = 1;
printf("%d\n", pcie_base[4]);
printf("\n\n");
printf("Sending write DMA\n");
printf("Sending read DMA\n");
pcie_base[8] = (uint32_t)dst_phys;
pcie_base[9] = (uint32_t)(dst_phys >> 32);
pcie_base[10] = dma_mem_addr;
pcie_base[11] = strlen(src);
for (int i = 8; i < 12; i++) {
printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
}
pcie_base[12] = 1;
printf("%d\n", pcie_base[12]);
printf("\n\n");
printf("strlen(dst)=%d\n", strlen(dst));
printf("%s\n", dst);
}