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Add eth dma wrapper

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This commit is contained in:
Byron Lathi
2025-11-15 12:49:52 -08:00
parent 31513dc16a
commit 4bd09e8f83
10 changed files with 546 additions and 35 deletions
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2
.gitignore vendored
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@@ -3,3 +3,5 @@
sim_build/
__pycache__/
clockInfo.txt

2
.gitmodules vendored
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@@ -1,3 +1,3 @@
[submodule "sub/taxi"]
path = sub/taxi
url = https://github.com/fpganinja/taxi.git
url = ../taxi.git

4
ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
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@@ -183,7 +183,7 @@
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "390.625", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -734,7 +734,7 @@
"C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CPLL_VCO_FREQUENCY": [ { "value": "2578.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FREERUN_FREQUENCY": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_FREERUN_FREQUENCY": [ { "value": "250", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],

2
sim/alibaba_pcie.yaml
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@@ -7,4 +7,4 @@ tests:
waves: True
defines:
SIM: ""
SIM: "1"

1
sources.list
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@@ -6,4 +6,5 @@ src/regs/verilator.vlt
src/regs/pcie_dma_regs_pkg.sv
src/regs/pcie_dma_regs.sv
src/pcie_dma_wrapper.sv
src/eth_dma_wrapper.sv
sub/taxi_sources.list

97
src/alibaba_pcie_top.sv
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@@ -20,17 +20,25 @@
//////////////////////////////////////////////////////////////////////////////////
module alibaba_pcie(
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
output wire [3:0] Led_o,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_reset_n,
input wire pcie_reset_n
input wire sfp_mgt_clk_p,
input wire sfp_mgt_clk_n,
output wire [1:0] sfp_txp,
output wire [1:0] sfp_txn,
input wire [1:0] sfp_rxp,
input wire [1:0] sfp_rxn,
output wire [3:0] Led_o
);
@@ -54,7 +62,9 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_axil_if m_axil_rd();
taxi_axil_if m_axil_wr();
taxi_apb_if #(.ADDR_W(6)) m_apb();
taxi_apb_if #(.ADDR_W(7)) s_apb();
taxi_apb_if #(.ADDR_W(6)) m_apb[2]();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
@@ -69,6 +79,50 @@ IBUFDS_GTE4 m_ibufds (
assign Led_o[0] = user_lnk_up;
assign Led_o[1] = phy_rdy_out;
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
taxi_apb_interconnect #(
.M_CNT(2),
.ADDR_W(7),
.M_REGIONS(1),
.M_BASE_ADDR('0),
.M_ADDR_W({32'd6, 32'd6}),
.M_SECURE({2{1'b0}})
) u_apb_interconnect (
.clk (clk_250),
.rst (rst_250),
.s_apb (s_apb),
.m_apb (m_apb)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_tx_psdpram (
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_pcie_wr_if),
.dma_ram_rd (dma_ram_eth_rd_if)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_rx_psdpram(
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_eth_wr_if),
.dma_ram_rd (dma_ram_pcie_rd_if)
);
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
@@ -93,7 +147,7 @@ taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
.s_axil_wr (m_axil_wr),
.s_axil_rd (m_axil_rd),
.m_apb (m_apb)
.m_apb (s_apb)
);
pcie_dma_wrapper u_pcie_dma_wrapper (
@@ -103,7 +157,28 @@ pcie_dma_wrapper u_pcie_dma_wrapper (
.m_axis_rq (s_axis_rq),
.s_axis_rc (m_axis_rc),
.s_apb (m_apb)
.wr_dma_mst (dma_ram_pcie_wr_if),
.rd_dma_mst (dma_ram_pcie_rd_if),
.s_apb (m_apb[0])
);
eth_dma_wrapper u_eth_dma_wrapper (
.clk_250 (clk_250),
.rst_250 (rst_250),
.sfp_mgt_clk_p (sfp_mgt_clk_p),
.sfp_mgt_clk_n (sfp_mgt_clk_n),
.sfp_txp (sfp_txp),
.sfp_txn (sfp_txn),
.sfp_rxp (sfp_rxp),
.sfp_rxn (sfp_rxn),
.wr_dma_mst (dma_ram_eth_wr_if),
.rd_dma_mst (dma_ram_eth_rd_if),
.s_apb (m_apb[1])
);
`ifndef SIM

425
src/eth_dma_wrapper.sv Normal file
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@@ -0,0 +1,425 @@
module eth_dma_wrapper (
input wire clk_250,
input wire rst_250,
input sfp_mgt_clk_p,
input sfp_mgt_clk_n,
output wire [1:0] sfp_txp,
output wire [1:0] sfp_txn,
input wire [1:0] sfp_rxp,
input wire [1:0] sfp_rxn,
taxi_dma_ram_if.wr_mst wr_dma_mst,
taxi_dma_ram_if.rd_mst rd_dma_mst,
taxi_apb_if.slv s_apb
);
wire mac_rx_clk[2];
wire mac_tx_clk[2];
wire mac_rx_rst[2];
wire mac_tx_rst[2];
wire sfp_mgt_refclk;
wire sfp_mgt_clk_int;
wire sfp_mgt_clk_bufg;
wire sfp_rst;
logic xcvr_gtpowergood;
`ifdef SIM
assign sfp_mgt_refclk = sfp_mgt_clk_p;
assign sfp_mgt_clk_int = sfp_mgt_clk_p;
assign sfp_mgt_clk_bufg = sfp_mgt_clk_int;
`else
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_clk_inst (
.I (sfp_mgt_clk_p),
.IB (sfp_mgt_clk_n),
.CEB (1'b0),
.O (sfp_mgt_refclk),
.ODIV2 (sfp_mgt_clk_int)
);
BUFG_GT bufg_gt_sfp_mgt_clk_inst (
.CE (&xcvr_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (sfp_mgt_clk_int),
.O (sfp_mgt_clk_bufg)
);
`endif
taxi_sync_reset #(
.N(4)
)
qsfp_sync_reset_inst (
.clk(sfp_mgt_clk_bufg),
.rst(rst_250),
.out(sfp_rst)
);
taxi_axis_if #(.DATA_W(64)) axis_tx_250();
taxi_axis_if #(.DATA_W(64)) mac_tx_axis[2]();
taxi_axis_if #(.DATA_W(64)) axis_rx_250();
taxi_axis_if #(.DATA_W(64)) mac_rx_axis[2]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
generate
for (genvar i = 0; i < 2; i++) begin
taxi_axis_null_snk u_tx_cpl_stub (
.s_axis(axis_sfp_tx_cpl[i])
);
end
endgenerate
taxi_axis_if axis_sfp_stat();
taxi_apb_if #(.DATA_W(16), .ADDR_W(17)) apb_mac_ctrl_stub ();
assign apb_mac_ctrl_stub.psel = '0;
assign apb_mac_ctrl_stub.penable = '0;
taxi_eth_mac_25g_us #(
.SIM(`SIM),
.VENDOR("XILINX"),
.FAMILY("kintexuplus"),
.CNT(2),
.CFG_LOW_LATENCY(0),
.GT_TYPE("GTY")
// leave all other parameters default for now
) u_taxi_eth_phy_25g_us (
.xcvr_ctrl_clk (clk_250),
.xcvr_ctrl_rst (sfp_rst),
.s_apb_ctrl (apb_mac_ctrl_stub),
.xcvr_gtpowergood_out (xcvr_gtpowergood),
.xcvr_gtrefclk00_in (sfp_mgt_refclk),
.xcvr_qpll0pd_in (1'b0),
.xcvr_qpll0reset_in (1'b0),
.xcvr_qpll0pcierate_in (3'd0),
.xcvr_qpll0lock_out (),
.xcvr_qpll0clk_out (),
.xcvr_qpll0refclk_out (),
.xcvr_gtrefclk01_in (sfp_mgt_refclk),
.xcvr_qpll1pd_in (1'b0),
.xcvr_qpll1reset_in (1'b0),
.xcvr_qpll1pcierate_in (3'd0),
.xcvr_qpll1lock_out (),
.xcvr_qpll1clk_out (),
.xcvr_qpll1refclk_out (),
.xcvr_txp ({sfp_txp[1], sfp_txp[0]}),
.xcvr_txn ({sfp_txn[1], sfp_txn[0]}),
.xcvr_rxp ({sfp_rxp[1], sfp_rxp[0]}),
.xcvr_rxn ({sfp_rxn[1], sfp_rxn[0]}),
.rx_clk (mac_rx_clk),
.rx_rst_in ('{2{'0}}),
.rx_rst_out (mac_rx_rst),
.tx_clk (mac_tx_clk),
.tx_rst_in ('{2{'0}}),
.tx_rst_out (mac_tx_rst),
.ptp_sample_clk ('{2{'0}}),
.s_axis_tx (mac_tx_axis), // TODO
.m_axis_tx_cpl (axis_sfp_tx_cpl), // TODO
.m_axis_rx (mac_rx_axis), // TODO
.tx_ptp_ts ('{2{'0}}),
.tx_ptp_ts_step ('{2{'0}}),
.rx_ptp_ts ('{2{'0}}),
.rx_ptp_ts_step ('{2{'0}}),
.tx_lfc_req ('{2{'0}}),
.tx_lfc_resend ('{2{'0}}),
.rx_lfc_en ('{2{'0}}),
.rx_lfc_req (),
.rx_lfc_ack ('{2{'0}}),
.tx_pfc_req ('{2{'0}}),
.tx_pfc_resend ('{2{'0}}),
.rx_pfc_en ('{2{'0}}),
.rx_pfc_req (),
.rx_pfc_ack ('{2{'0}}),
.tx_lfc_pause_en ('{2{'0}}),
.tx_pause_req ('{2{'0}}),
.tx_pause_ack (),
.stat_clk (clk_250),
.stat_rst (rst_250),
.m_axis_stat (axis_sfp_stat),
// all of these stats should really be in a registerfile
.tx_start_packet (),
.stat_tx_byte (),
.stat_tx_pkt_len (),
.stat_tx_pkt_ucast (),
.stat_tx_pkt_mcast (),
.stat_tx_pkt_bcast (),
.stat_tx_pkt_vlan (),
.stat_tx_pkt_good (),
.stat_tx_pkt_bad (),
.stat_tx_err_oversize (),
.stat_tx_err_user (),
.stat_tx_err_underflow (),
.rx_start_packet (),
.rx_error_count (),
.rx_block_lock (),
.rx_high_ber (),
.rx_status (),
.stat_rx_byte (),
.stat_rx_pkt_len (),
.stat_rx_pkt_fragment (),
.stat_rx_pkt_jabber (),
.stat_rx_pkt_ucast (),
.stat_rx_pkt_mcast (),
.stat_rx_pkt_bcast (),
.stat_rx_pkt_vlan (),
.stat_rx_pkt_good (),
.stat_rx_pkt_bad (),
.stat_rx_err_oversize (),
.stat_rx_err_bad_fcs (),
.stat_rx_err_bad_block (),
.stat_rx_err_framing (),
.stat_rx_err_preamble (),
.stat_rx_fifo_drop ('{2{1'b0}}),
.stat_tx_mcf (),
.stat_rx_mcf (),
.stat_tx_lfc_pkt (),
.stat_tx_lfc_xon (),
.stat_tx_lfc_xoff (),
.stat_tx_lfc_paused (),
.stat_tx_pfc_pkt (),
.stat_tx_pfc_xon (),
.stat_tx_pfc_xoff (),
.stat_tx_pfc_paused (),
.stat_rx_lfc_pkt (),
.stat_rx_lfc_xon (),
.stat_rx_lfc_xoff (),
.stat_rx_lfc_paused (),
.stat_rx_pfc_pkt (),
.stat_rx_pfc_xon (),
.stat_rx_pfc_xoff (),
.stat_rx_pfc_paused (),
// all of these configs should really be in a registerfile
.cfg_tx_max_pkt_len ('{2{16'd1518}}),
.cfg_tx_ifg ('{2{8'd12}}),
.cfg_tx_enable ('{2{1'b1}}),
.cfg_rx_max_pkt_len ('{2{16'd1518}}),
.cfg_rx_enable ('{2{1'b1}}),
.cfg_ifg ('{2{8'd12}}),
.cfg_tx_prbs31_enable ('{2{1'b0}}),
.cfg_rx_prbs31_enable ('{2{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast ('{2{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast ('{2{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast ('{2{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast ('{2{1'b0}}),
.cfg_mcf_rx_eth_src ('{2{48'd0}}),
.cfg_mcf_rx_check_eth_src ('{2{1'b0}}),
.cfg_mcf_rx_eth_type ('{2{16'h8808}}),
.cfg_mcf_rx_opcode_lfc ('{2{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc ('{2{1'b1}}),
.cfg_mcf_rx_opcode_pfc ('{2{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc ('{2{1'b1}}),
.cfg_mcf_rx_forward ('{2{1'b0}}),
.cfg_mcf_rx_enable ('{2{1'b0}}),
.cfg_tx_lfc_eth_dst ('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src ('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type ('{2{16'h8808}}),
.cfg_tx_lfc_opcode ('{2{16'h0001}}),
.cfg_tx_lfc_en ('{2{1'b0}}),
.cfg_tx_lfc_quanta ('{2{16'hffff}}),
.cfg_tx_lfc_refresh ('{2{16'h7fff}}),
.cfg_tx_pfc_eth_dst ('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src ('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type ('{2{16'h8808}}),
.cfg_tx_pfc_opcode ('{2{16'h0101}}),
.cfg_tx_pfc_en ('{2{1'b0}}),
.cfg_tx_pfc_quanta ('{2{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh ('{2{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode ('{2{16'h0001}}),
.cfg_rx_lfc_en ('{2{1'b0}}),
.cfg_rx_pfc_opcode ('{2{16'h0101}}),
.cfg_rx_pfc_en ('{2{1'b0}})
);
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) rd_desc();
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) wr_desc();
pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out;
pcie_dma_regs u_pcie_dma_regs(
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (s_apb.psel),
.s_apb_penable (s_apb.penable),
.s_apb_pwrite (s_apb.pwrite),
.s_apb_pprot (s_apb.pprot),
.s_apb_paddr (s_apb.paddr),
.s_apb_pwdata (s_apb.pwdata),
.s_apb_pstrb (s_apb.pstrb),
.s_apb_pready (s_apb.pready),
.s_apb_prdata (s_apb.prdata),
.s_apb_pslverr (s_apb.pslverr),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
);
logic [7:0] read_tag;
logic [7:0] write_tag;
always_ff @(posedge clk_250) begin
if (rst_250) begin
read_tag <= '0;
write_tag <= '0;
end else begin
if (rd_desc.req_valid && rd_desc.req_ready) begin
read_tag <= read_tag + 1;
end
if (wr_desc.req_valid && wr_desc.req_ready) begin
write_tag <= write_tag + 1;
end
end
end
always_comb begin
rd_desc.req_src_addr = hwif_out.dma_rd.src_addr_low.addr.value[15:0];
rd_desc.req_src_sel = '0;
rd_desc.req_dst_addr = hwif_out.dma_rd.dst_addr.addr.value;
rd_desc.req_dst_sel = '0;
rd_desc.req_imm = '0;
rd_desc.req_imm_en = '0;
rd_desc.req_len = hwif_out.dma_rd.length.len.value;
rd_desc.req_tag = read_tag;
rd_desc.req_id = '0;
rd_desc.req_dest = '0;
rd_desc.req_user = '0;
rd_desc.req_valid = hwif_out.dma_rd.trigger.trigger.value;
hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
wr_desc.req_src_addr = hwif_out.dma_wr.src_addr.addr.value;
wr_desc.req_src_sel = '0;
wr_desc.req_dst_addr = hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
wr_desc.req_dst_sel = '0;
wr_desc.req_imm = '0;
wr_desc.req_imm_en = '0;
wr_desc.req_len = hwif_out.dma_wr.length.len.value;
wr_desc.req_tag = write_tag;
wr_desc.req_id = '0;
wr_desc.req_dest = '0;
wr_desc.req_user = '0;
wr_desc.req_valid = hwif_out.dma_wr.trigger.trigger.value;
hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
end
// 250 is too slow to actually saturate 25Gbps, but
// the DMA is not supposed to saturate it anyway
taxi_dma_client_axis_sink u_taxi_dma_client_axis_sink (
.clk (clk_250),
.rst (rst_250),
.desc_req (wr_desc),
.desc_sts (wr_desc),
.s_axis_wr_data (axis_rx_250),
.dma_ram_wr (wr_dma_mst),
.enable ('1),
.abort ('0)
);
taxi_dma_client_axis_source u_taxi_dma_client_axis_source (
.clk (clk_250),
.rst (rst_250),
.desc_req (rd_desc),
.desc_sts (rd_desc),
.m_axis_rd_data (axis_tx_250),
.dma_ram_rd (rd_dma_mst),
.enable ('1)
);
taxi_axis_async_fifo #(
.FRAME_FIFO('1)
) u_rx_async_saf (
.s_clk (mac_rx_clk[1]),
.s_rst (mac_rx_rst[1]),
.s_axis (mac_rx_axis[1]),
.m_clk (clk_250),
.m_rst (rst_250),
.m_axis (axis_rx_250),
.s_pause_req ('0),
.s_pause_ack (),
.m_pause_req ('0),
.m_pause_ack (),
.s_status_depth (),
.s_status_depth_commit (),
.s_status_overflow (),
.s_status_bad_frame (),
.s_status_good_frame (),
.m_status_depth (),
.m_status_depth_commit (),
.m_status_overflow (),
.m_status_bad_frame (),
.m_status_good_frame ()
);
taxi_axis_async_fifo #(
.FRAME_FIFO('1)
) u_tx_async_saf (
.s_clk (clk_250),
.s_rst (rst_250),
.s_axis (axis_tx_250),
.m_clk (mac_tx_clk[0]),
.m_rst (mac_tx_rst[0]),
.m_axis (mac_tx_axis[0]),
.s_pause_req ('0),
.s_pause_ack (),
.m_pause_req ('0),
.m_pause_ack (),
.s_status_depth (),
.s_status_depth_commit (),
.s_status_overflow (),
.s_status_bad_frame (),
.s_status_good_frame (),
.m_status_depth (),
.m_status_depth_commit (),
.m_status_overflow (),
.m_status_bad_frame (),
.m_status_good_frame ()
);
endmodule

20
src/pcie_dma_wrapper.sv
View File

@@ -5,6 +5,9 @@ module pcie_dma_wrapper (
taxi_axis_if.src m_axis_rq,
taxi_axis_if.snk s_axis_rc,
taxi_dma_ram_if.wr_mst wr_dma_mst,
taxi_dma_ram_if.rd_mst rd_dma_mst,
taxi_apb_if.slv s_apb
);
@@ -18,9 +21,6 @@ logic seq_num_valid_1;
taxi_dma_desc_if #(.DST_ADDR_W(16)) rd_desc();
taxi_dma_desc_if #(.SRC_ADDR_W(16)) wr_desc();
// the dma just reads and writes from the same memory
taxi_dma_ram_if #(.SEGS(4)) dma_ram_if();
pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out;
@@ -43,16 +43,6 @@ pcie_dma_regs u_pcie_dma_regs(
.hwif_out (hwif_out)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_psdpram (
.clk (clk),
.rst (rst),
.dma_ram_wr (dma_ram_if),
.dma_ram_rd (dma_ram_if)
);
logic [7:0] read_tag;
logic [7:0] write_tag;
@@ -131,8 +121,8 @@ taxi_dma_if_pcie_us #(
.wr_desc_req (wr_desc),
.wr_desc_sts (wr_desc),
.dma_ram_wr (dma_ram_if),
.dma_ram_rd (dma_ram_if),
.dma_ram_wr (wr_dma_mst),
.dma_ram_rd (rd_dma_mst),
.read_enable ('1),
.write_enable ('1),

2
sub/taxi

Submodule sub/taxi updated: c6eac348f6...729bf79427

24
sub/taxi_sources.list
View File

@@ -1,3 +1,8 @@
taxi/src/apb/rtl/taxi_apb_adapter.sv
taxi/src/apb/rtl/taxi_apb_dp_ram.sv
taxi/src/apb/rtl/taxi_apb_if.sv
taxi/src/apb/rtl/taxi_apb_interconnect.sv
taxi/src/apb/rtl/taxi_apb_ram.sv
taxi/src/axi/rtl/taxi_axi_if.sv
taxi/src/axi/rtl/taxi_axil_register_wr.sv
taxi/src/axi/rtl/taxi_axi_axil_adapter.sv
@@ -59,6 +64,7 @@ taxi/src/axis/rtl/taxi_axis_arb_mux.f
taxi/src/axis/rtl/taxi_axis_null_src.sv
#taxi/src/axis/rtl/taxi_axis_switch.sv
taxi/src/axis/rtl/taxi_axis_fifo.sv
taxi/src/axis/syn/vivado/taxi_axis_async_fifo.tcl
taxi/src/pcie/rtl/taxi_pcie_us_axil_master.sv
taxi/src/pcie/rtl/taxi_pcie_tlp_if.sv
taxi/src/pcie/rtl/taxi_pcie_axil_master.sv
@@ -82,9 +88,6 @@ taxi/src/dma/rtl/taxi_dma_if_pcie_us_wr.sv
taxi/src/dma/rtl/taxi_dma_psdpram.sv
taxi/src/dma/rtl/taxi_dma_psdpram_async.sv
taxi/src/dma/rtl/taxi_dma_ram_if.sv
taxi/src/apb/rtl/taxi_apb_dp_ram.sv
taxi/src/apb/rtl/taxi_apb_if.sv
taxi/src/apb/rtl/taxi_apb_ram.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
taxi/src/eth/rtl/taxi_axis_gmii_rx.sv
@@ -128,8 +131,23 @@ taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
taxi/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
taxi/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
taxi/src/eth/rtl/taxi_axis_xgmii_tx_32.sv
taxi/src/eth/rtl/taxi_eth_mac_stats.sv
taxi/src/eth/rtl/taxi_rgmii_phy_if.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx.sv
taxi/src/lfsr/rtl/taxi_lfsr_crc.sv
taxi/src/lfsr/rtl/taxi_lfsr_descramble.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_check.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv
taxi/src/lfsr/rtl/taxi_lfsr_scramble.sv
taxi/src/lfsr/rtl/taxi_lfsr.sv
taxi/src/sync/rtl/taxi_sync_reset.sv
taxi/src/sync/rtl/taxi_sync_signal.sv
taxi/src/sync/syn/vivado/taxi_sync_reset.tcl
taxi/src/sync/syn/vivado/taxi_sync_signal.tcl
taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
taxi/src/hip/rtl/us/taxi_mmcm_frac.sv