eth: Move link speed detection logic from MAC wrapper to PHY interface

Signed-off-by: Alex Forencich <alex@alexforencich.com>

.github/workflows/regression-tests.yml

@@ -21,7 +21,7 @@ jobs:
     - name: Install Verilator
       uses: v0xnihili/install-verilator-action@main
       with:
-        version: v5.034
+        version: v5.038
 
     - name: Install Python dependencies
       run: |

.gitignore

@@ -5,3 +5,5 @@
 *.pyc
 *.vvp
 
+sim_build
+results.xml

README.md

@@ -26,11 +26,15 @@ To facilitate the dual-license model, contributions to the project can only be a
 
 *  APB
     *  SV interface for APB
+    *  Interconnect
+    *  Width converter
     *  Single-port RAM
     *  Dual-port RAM
 *  AXI
     *  SV interface for AXI
     *  AXI to AXI lite adapter
+    *  Crossbar
+    *  Interconnect
     *  Register slice
     *  Width converter
     *  Synchronous FIFO
@@ -39,6 +43,8 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  SV interface for AXI lite
     *  AXI lite to AXI adapter
     *  AXI lite to APB adapter
+    *  Crossbar
+    *  Interconnect
     *  Register slice
     *  Width converter
     *  Single-port RAM
@@ -87,7 +93,7 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  MII PHY interface
     *  GMII PHY interface
     *  RGMII PHY interface
-    *  10G/25G MAC/PHY/GT wrapper for UltraScale/UltraScale+
+    *  10G/25G MAC/PHY/GT wrapper for 7-series/UltraScale/UltraScale+
 *  General input/output
     *  Switch debouncer
     *  LED shift register driver
@@ -156,6 +162,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
 *  Alibaba AS02MC04 (Xilinx Kintex UltraScale+ XCKU3P)
 *  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
+*  Digilent NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
 *  HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
 *  HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
 *  HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
@@ -172,6 +179,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
 *  Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
+*  Xilinx VC709 (Xilinx Virtex 7 XC7V690T)
 *  Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
 *  Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
 *  Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)

src/apb/rtl/taxi_apb_adapter.sv

@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB width adapter
+ */
+module taxi_apb_adapter
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * APB slave interface
+     */
+    taxi_apb_if.slv    s_apb,
+
+    /*
+     * APB master interface
+     */
+    taxi_apb_if.mst    m_apb
+);
+
+// extract parameters
+localparam S_DATA_W = s_apb.DATA_W;
+localparam ADDR_W = s_apb.ADDR_W;
+localparam S_STRB_W = s_apb.STRB_W;
+localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb.PAUSER_EN;
+localparam PAUSER_W = s_apb.PAUSER_W;
+localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb.PWUSER_EN;
+localparam PWUSER_W = s_apb.PWUSER_W;
+localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb.PRUSER_EN;
+localparam PRUSER_W = s_apb.PRUSER_W;
+localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb.PBUSER_EN;
+localparam PBUSER_W = s_apb.PBUSER_W;
+
+localparam M_DATA_W = m_apb.DATA_W;
+localparam M_STRB_W = m_apb.STRB_W;
+
+localparam S_ADDR_BIT_OFFSET = $clog2(S_STRB_W);
+localparam M_ADDR_BIT_OFFSET = $clog2(M_STRB_W);
+localparam S_BYTE_LANES = S_STRB_W;
+localparam M_BYTE_LANES = M_STRB_W;
+localparam S_BYTE_W = S_DATA_W/S_BYTE_LANES;
+localparam M_BYTE_W = M_DATA_W/M_BYTE_LANES;
+localparam S_ADDR_MASK = {ADDR_W{1'b1}} << S_ADDR_BIT_OFFSET;
+localparam M_ADDR_MASK = {ADDR_W{1'b1}} << M_ADDR_BIT_OFFSET;
+
+// check configuration
+if (S_BYTE_W * S_STRB_W != S_DATA_W)
+    $fatal(0, "Error: APB slave interface data width not evenly divisible (instance %m)");
+
+if (M_BYTE_W * M_STRB_W != M_DATA_W)
+    $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)");
+
+if (S_BYTE_W != M_BYTE_W)
+    $fatal(0, "Error: byte size mismatch (instance %m)");
+
+if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES)
+    $fatal(0, "Error: APB slave interface byte lane count must be even power of two (instance %m)");
+
+if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES)
+    $fatal(0, "Error: APB master interface byte lane count must be even power of two (instance %m)");
+
+if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
+    // same width; bypass
+
+    assign m_apb.paddr = s_apb.paddr;
+    assign m_apb.pprot = s_apb.pprot;
+    assign m_apb.psel = s_apb.psel;
+    assign m_apb.penable = s_apb.penable;
+    assign m_apb.pwrite = s_apb.pwrite;
+    assign m_apb.pwdata = s_apb.pwdata;
+    assign m_apb.pstrb = s_apb.pstrb;
+    assign s_apb.pready = m_apb.pready;
+    assign s_apb.prdata = m_apb.prdata;
+    assign s_apb.pslverr = m_apb.pslverr;
+    assign m_apb.pauser = PAUSER_EN ? s_apb.pauser : '0;
+    assign m_apb.pwuser = PWUSER_EN ? s_apb.pwuser : '0;
+    assign s_apb.pruser = PRUSER_EN ? m_apb.pruser : '0;
+    assign s_apb.pbuser = PBUSER_EN ? m_apb.pbuser : '0;
+
+end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
+    // output is wider; upsize
+
+    localparam [0:0]
+        STATE_IDLE = 1'd0,
+        STATE_DATA = 1'd1;
+
+    logic [0:0] state_reg = STATE_IDLE, state_next;
+
+    logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
+    logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
+    logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
+    logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
+    logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
+
+    logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
+    logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
+    logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
+    logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
+    logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
+    logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
+    logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
+    logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
+    logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
+
+    assign s_apb.pready = s_apb_pready_reg;
+    assign s_apb.prdata = s_apb_prdata_reg;
+    assign s_apb.pslverr = s_apb_pslverr_reg;
+    assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+    assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+    assign m_apb.paddr = m_apb_paddr_reg;
+    assign m_apb.pprot = m_apb_pprot_reg;
+    assign m_apb.psel = m_apb_psel_reg;
+    assign m_apb.penable = m_apb_penable_reg;
+    assign m_apb.pwrite = m_apb_pwrite_reg;
+    assign m_apb.pwdata = m_apb_pwdata_reg;
+    assign m_apb.pstrb = m_apb_pstrb_reg;
+    assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+
+    always_comb begin
+        state_next = STATE_IDLE;
+
+        s_apb_pready_next = 1'b0;
+        s_apb_prdata_next = s_apb_prdata_reg;
+        s_apb_pslverr_next = s_apb_pslverr_reg;
+        s_apb_pruser_next = s_apb_pruser_reg;
+        s_apb_pbuser_next = s_apb_pbuser_reg;
+
+        m_apb_paddr_next = m_apb_paddr_reg;
+        m_apb_pprot_next = m_apb_pprot_reg;
+        m_apb_psel_next = 1'b0;
+        m_apb_penable_next = 1'b0;
+        m_apb_pwrite_next = m_apb_pwrite_reg;
+        m_apb_pwdata_next = m_apb_pwdata_reg;
+        m_apb_pstrb_next = m_apb_pstrb_reg;
+        m_apb_pauser_next = m_apb_pauser_reg;
+        m_apb_pwuser_next = m_apb_pwuser_reg;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                m_apb_paddr_next = s_apb.paddr;
+                m_apb_pprot_next = s_apb.pprot;
+                m_apb_pwrite_next = s_apb.pwrite;
+                m_apb_pwdata_next = {(M_BYTE_LANES/S_BYTE_LANES){s_apb.pwdata}};
+                m_apb_pstrb_next = '0;
+                m_apb_pstrb_next[s_apb.paddr[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_STRB_W +: S_STRB_W] = s_apb.pstrb;
+                m_apb_pauser_next = s_apb.pauser;
+                m_apb_pwuser_next = s_apb.pwuser;
+
+                if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
+                    m_apb_psel_next = 1'b1;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_apb_psel_next = 1'b1;
+                m_apb_penable_next = 1'b1;
+
+                s_apb_pready_next = 1'b0;
+                s_apb_prdata_next = m_apb.prdata[m_apb_paddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W];
+                s_apb_pslverr_next = m_apb.pslverr;
+                s_apb_pruser_next = m_apb.pruser;
+                s_apb_pbuser_next = m_apb.pbuser;
+
+                if (m_apb.psel && m_apb.penable && m_apb.pready) begin
+                    m_apb_psel_next = 1'b0;
+                    m_apb_penable_next = 1'b0;
+                    s_apb_pready_next = 1'b1;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+
+    always_ff @(posedge clk) begin
+        state_reg <= state_next;
+
+        s_apb_pready_reg <= s_apb_pready_next;
+        s_apb_prdata_reg <= s_apb_prdata_next;
+        s_apb_pslverr_reg <= s_apb_pslverr_next;
+        s_apb_pruser_reg <= s_apb_pruser_next;
+        s_apb_pbuser_reg <= s_apb_pbuser_next;
+
+        m_apb_paddr_reg <= m_apb_paddr_next;
+        m_apb_pprot_reg <= m_apb_pprot_next;
+        m_apb_psel_reg <= m_apb_psel_next;
+        m_apb_penable_reg <= m_apb_penable_next;
+        m_apb_pwrite_reg <= m_apb_pwrite_next;
+        m_apb_pwdata_reg <= m_apb_pwdata_next;
+        m_apb_pstrb_reg <= m_apb_pstrb_next;
+        m_apb_pauser_reg <= m_apb_pauser_next;
+        m_apb_pwuser_reg <= m_apb_pwuser_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+
+            s_apb_pready_reg <= 1'b0;
+
+            m_apb_psel_reg <= 1'b0;
+            m_apb_penable_reg <= 1'b0;
+        end
+    end
+
+end else begin : downsize
+    // output is narrower; downsize
+
+    // output bus is wider
+    localparam DATA_W = S_DATA_W;
+    localparam STRB_W = S_STRB_W;
+    // required number of segments in wider bus
+    localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
+    localparam SEG_COUNT_W = $clog2(SEG_COUNT);
+    // data width and keep width per segment
+    localparam SEG_DATA_W = DATA_W / SEG_COUNT;
+    localparam SEG_STRB_W = STRB_W / SEG_COUNT;
+
+    localparam [0:0]
+        STATE_IDLE = 1'd0,
+        STATE_DATA = 1'd1;
+
+    logic [0:0] state_reg = STATE_IDLE, state_next;
+
+    logic [DATA_W-1:0] data_reg = '0, data_next;
+    logic [STRB_W-1:0] strb_reg = '0, strb_next;
+
+    logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
+
+    logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
+    logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
+    logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
+    logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
+    logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
+
+    logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
+    logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
+    logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
+    logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
+    logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
+    logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
+    logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
+    logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
+    logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
+
+    assign s_apb.pready = s_apb_pready_reg;
+    assign s_apb.prdata = s_apb_prdata_reg;
+    assign s_apb.pslverr = s_apb_pslverr_reg;
+    assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+    assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+    assign m_apb.paddr = m_apb_paddr_reg;
+    assign m_apb.pprot = m_apb_pprot_reg;
+    assign m_apb.psel = m_apb_psel_reg;
+    assign m_apb.penable = m_apb_penable_reg;
+    assign m_apb.pwrite = m_apb_pwrite_reg;
+    assign m_apb.pwdata = m_apb_pwdata_reg;
+    assign m_apb.pstrb = m_apb_pstrb_reg;
+    assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+
+    always_comb begin
+        state_next = STATE_IDLE;
+
+        data_next = data_reg;
+        strb_next = strb_reg;
+
+        current_seg_next = current_seg_reg;
+
+        s_apb_pready_next = 1'b0;
+        s_apb_prdata_next = s_apb_prdata_reg;
+        s_apb_pslverr_next = s_apb_pslverr_reg;
+        s_apb_pruser_next = s_apb_pruser_reg;
+        s_apb_pbuser_next = s_apb_pbuser_reg;
+
+        m_apb_paddr_next = m_apb_paddr_reg;
+        m_apb_pprot_next = m_apb_pprot_reg;
+        m_apb_psel_next = 1'b0;
+        m_apb_penable_next = 1'b0;
+        m_apb_pwrite_next = m_apb_pwrite_reg;
+        m_apb_pwdata_next = m_apb_pwdata_reg;
+        m_apb_pstrb_next = m_apb_pstrb_reg;
+        m_apb_pauser_next = m_apb_pauser_reg;
+        m_apb_pwuser_next = m_apb_pwuser_reg;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                current_seg_next = s_apb.paddr[M_ADDR_BIT_OFFSET +: SEG_COUNT_W];
+
+                m_apb_paddr_next = s_apb.paddr;
+                m_apb_pprot_next = s_apb.pprot;
+                m_apb_pwrite_next = s_apb.pwrite;
+                data_next = s_apb.pwdata;
+                strb_next = s_apb.pstrb;
+                m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
+                m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
+                m_apb_pauser_next = s_apb.pauser;
+                m_apb_pwuser_next = s_apb.pwuser;
+
+                s_apb_pslverr_next = 1'b0;
+
+                if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
+                    m_apb_psel_next = 1'b1;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_apb_psel_next = 1'b1;
+                m_apb_penable_next = 1'b1;
+
+                s_apb_pready_next = 1'b0;
+                s_apb_prdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_apb.prdata;
+                if (m_apb.pslverr) begin
+                    s_apb_pslverr_next = 1'b1;
+                end
+                s_apb_pruser_next = m_apb.pruser;
+                s_apb_pbuser_next = m_apb.pbuser;
+
+                if (m_apb.psel && m_apb.penable && m_apb.pready) begin
+                    m_apb_penable_next = 1'b0;
+                    current_seg_next = current_seg_reg + 1;
+                    m_apb_paddr_next = (m_apb_paddr_reg & M_ADDR_MASK) + SEG_STRB_W;
+                    m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
+                    m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
+                    if (current_seg_reg == SEG_COUNT_W'(SEG_COUNT-1)) begin
+                        m_apb_psel_next = 1'b0;
+                        s_apb_pready_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+
+    always_ff @(posedge clk) begin
+        state_reg <= state_next;
+
+        data_reg <= data_next;
+        strb_reg <= strb_next;
+
+        current_seg_reg <= current_seg_next;
+
+        s_apb_pready_reg <= s_apb_pready_next;
+        s_apb_prdata_reg <= s_apb_prdata_next;
+        s_apb_pslverr_reg <= s_apb_pslverr_next;
+        s_apb_pruser_reg <= s_apb_pruser_next;
+        s_apb_pbuser_reg <= s_apb_pbuser_next;
+
+        m_apb_paddr_reg <= m_apb_paddr_next;
+        m_apb_pprot_reg <= m_apb_pprot_next;
+        m_apb_psel_reg <= m_apb_psel_next;
+        m_apb_penable_reg <= m_apb_penable_next;
+        m_apb_pwrite_reg <= m_apb_pwrite_next;
+        m_apb_pwdata_reg <= m_apb_pwdata_next;
+        m_apb_pstrb_reg <= m_apb_pstrb_next;
+        m_apb_pauser_reg <= m_apb_pauser_next;
+        m_apb_pwuser_reg <= m_apb_pwuser_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+
+            s_apb_pready_reg <= 1'b0;
+
+            m_apb_psel_reg <= 1'b0;
+            m_apb_penable_reg <= 1'b0;
+        end
+    end
+
+end
+
+endmodule
+
+`resetall

src/apb/rtl/taxi_apb_interconnect.sv

@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB interconnect
+ */
+module taxi_apb_interconnect #
+(
+    // Number of downstream APB interfaces
+    parameter M_CNT = 4,
+    // Width of address decoder in bits
+    parameter ADDR_W = 16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_CNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_CNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_CNT bits
+    parameter M_SECURE = {M_CNT{1'b0}}
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * APB slave interface
+     */
+    taxi_apb_if.slv                 s_apb,
+
+    /*
+     * APB master interface
+     */
+    taxi_apb_if.mst                 m_apb[M_CNT]
+);
+
+// extract parameters
+localparam DATA_W = s_apb.DATA_W;
+localparam S_ADDR_W = s_apb.ADDR_W;
+localparam STRB_W = s_apb.STRB_W;
+localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb[0].PAUSER_EN;
+localparam PAUSER_W = s_apb.PAUSER_W;
+localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb[0].PWUSER_EN;
+localparam PWUSER_W = s_apb.PWUSER_W;
+localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb[0].PRUSER_EN;
+localparam PRUSER_W = s_apb.PRUSER_W;
+localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb[0].PBUSER_EN;
+localparam PBUSER_W = s_apb.PBUSER_W;
+
+localparam APB_M_ADDR_W = m_apb[0].ADDR_W;
+
+localparam CL_M_CNT = $clog2(M_CNT);
+localparam CL_M_CNT_INT = CL_M_CNT > 0 ? CL_M_CNT : 1;
+
+localparam [M_CNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_CNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_CNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_CNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_CNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_apb.ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_apb[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_apb[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for apb_interconnect instance %m");
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_CNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+logic [CL_M_CNT_INT-1:0] sel_reg = '0;
+logic act_reg = 1'b0;
+
+logic s_apb_pready_reg = 1'b0;
+logic [DATA_W-1:0] s_apb_prdata_reg = '0;
+logic s_apb_pslverr_reg = 1'b0;
+logic [PRUSER_W-1:0] s_apb_pruser_reg = '0;
+logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0;
+
+logic [ADDR_W-1:0] m_apb_paddr_reg = '0;
+logic [2:0] m_apb_pprot_reg = '0;
+logic [M_CNT-1:0] m_apb_psel_reg = '0;
+logic m_apb_penable_reg = 1'b0;
+logic m_apb_pwrite_reg = 1'b0;
+logic [DATA_W-1:0] m_apb_pwdata_reg = '0;
+logic [STRB_W-1:0] m_apb_pstrb_reg = '0;
+logic [PAUSER_W-1:0] m_apb_pauser_reg = '0;
+logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0;
+
+wire [M_CNT-1:0] m_apb_pready;
+wire [DATA_W-1:0] m_apb_prdata[M_CNT];
+wire m_apb_pslverr[M_CNT];
+wire [PRUSER_W-1:0] m_apb_pruser[M_CNT];
+wire [PBUSER_W-1:0] m_apb_pbuser[M_CNT];
+
+assign s_apb.pready = s_apb_pready_reg;
+assign s_apb.prdata = s_apb_prdata_reg;
+assign s_apb.pslverr = s_apb_pslverr_reg;
+assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+for (genvar n = 0; n < M_CNT; n += 1) begin
+    assign m_apb[n].paddr = APB_M_ADDR_W'(m_apb_paddr_reg);
+    assign m_apb[n].pprot = m_apb_pprot_reg;
+    assign m_apb[n].psel = m_apb_psel_reg[n];
+    assign m_apb[n].penable = m_apb_penable_reg;
+    assign m_apb[n].pwrite = m_apb_pwrite_reg;
+    assign m_apb[n].pwdata = m_apb_pwdata_reg;
+    assign m_apb[n].pstrb = m_apb_pstrb_reg;
+    assign m_apb_pready[n] = m_apb[n].pready;
+    assign m_apb_prdata[n] = m_apb[n].prdata;
+    assign m_apb_pslverr[n] = m_apb[n].pslverr;
+    assign m_apb[n].pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb[n].pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+    assign m_apb_pruser[n] = m_apb[n].pruser;
+    assign m_apb_pbuser[n] = m_apb[n].pbuser;
+end
+
+always_ff @(posedge clk) begin
+    s_apb_pready_reg <= 1'b0;
+    m_apb_penable_reg <= act_reg && s_apb.penable;
+
+    s_apb_prdata_reg <= m_apb_prdata[sel_reg];
+    s_apb_pslverr_reg <= m_apb_pslverr[sel_reg] | (m_apb_psel_reg == 0);
+    s_apb_pruser_reg <= m_apb_pruser[sel_reg];
+    s_apb_pbuser_reg <= m_apb_pbuser[sel_reg];
+
+    if ((m_apb_psel_reg & ~m_apb_pready) == 0) begin
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+        s_apb_pready_reg <= act_reg;
+        act_reg <= 1'b0;
+    end
+
+    if (!act_reg) begin
+        m_apb_paddr_reg <= s_apb.paddr;
+        m_apb_pprot_reg <= s_apb.pprot;
+        m_apb_pwrite_reg <= s_apb.pwrite;
+        m_apb_pwdata_reg <= s_apb.pwdata;
+        m_apb_pstrb_reg <= s_apb.pstrb;
+        m_apb_pauser_reg <= s_apb.pauser;
+        m_apb_pwuser_reg <= s_apb.pwuser;
+
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+
+        if (s_apb.psel && s_apb.penable && !s_apb_pready_reg) begin
+            act_reg <= 1'b1;
+            for (integer i = 0; i < M_CNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_apb.pprot[1]) && (s_apb.paddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        sel_reg <= CL_M_CNT_INT'(i);
+                        m_apb_psel_reg[i] <= 1'b1;
+                    end
+                end
+            end
+        end
+    end
+
+    if (rst) begin
+        act_reg <= 1'b0;
+        s_apb_pready_reg <= 1'b0;
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/apb/tb/taxi_apb_adapter/Makefile

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_apb_adapter
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_ADDR_W := 32
+export PARAM_S_DATA_W := 32
+export PARAM_S_STRB_W := $(shell expr $(PARAM_S_DATA_W) / 8 )
+export PARAM_M_DATA_W := 32
+export PARAM_M_STRB_W := $(shell expr $(PARAM_M_DATA_W) / 8 )
+export PARAM_PAUSER_EN := 0
+export PARAM_PAUSER_W := 1
+export PARAM_PWUSER_EN := 0
+export PARAM_PWUSER_W := 1
+export PARAM_PBUSER_EN := 0
+export PARAM_PBUSER_W := 1
+export PARAM_PRUSER_EN := 0
+export PARAM_PRUSER_W := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.py

@@ -0,0 +1,237 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import ApbBus, ApbMaster, ApbRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
+        self.apb_ram = ApbRam(ApbBus.from_entity(dut.m_apb), dut.clk, dut.rst, size=2**16)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.apb_master.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.apb_ram.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram.write(addr-128, b'\xaa'*(length+256))
+
+            await tb.apb_master.write(addr, test_data)
+
+            tb.log.debug("%s", tb.apb_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.apb_ram.read(addr, length) == test_data
+            assert tb.apb_ram.read(addr-1, 1) == b'\xaa'
+            assert tb.apb_ram.read(addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram.write(addr, test_data)
+
+            data = await tb.apb_master.read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length)
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.apb_master, k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("m_data_w", [8, 16, 32])
+@pytest.mark.parametrize("s_data_w", [8, 16, 32])
+def test_taxi_apb_adapter(request, s_data_w, m_data_w):
+    dut = "taxi_apb_adapter"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_apb_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['ADDR_W'] = 32
+    parameters['S_DATA_W'] = s_data_w
+    parameters['S_STRB_W'] = parameters['S_DATA_W'] // 8
+    parameters['M_DATA_W'] = m_data_w
+    parameters['M_STRB_W'] = parameters['M_DATA_W'] // 8
+    parameters["PAUSER_EN"] = 0
+    parameters["PAUSER_W"] = 1
+    parameters["PWUSER_EN"] = 0
+    parameters["PWUSER_W"] = 1
+    parameters["PRUSER_EN"] = 0
+    parameters["PRUSER_W"] = 1
+    parameters["PBUSER_EN"] = 0
+    parameters["PBUSER_W"] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB width adapter testbench
+ */
+module test_taxi_apb_adapter #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter ADDR_W = 32,
+    parameter S_DATA_W = 32,
+    parameter S_STRB_W = (S_DATA_W/8),
+    parameter M_DATA_W = 32,
+    parameter M_STRB_W = (M_DATA_W/8),
+    parameter logic PAUSER_EN = 1'b0,
+    parameter PAUSER_W = 1,
+    parameter logic PWUSER_EN = 1'b0,
+    parameter PWUSER_W = 1,
+    parameter logic PRUSER_EN = 1'b0,
+    parameter PRUSER_W = 1,
+    parameter logic PBUSER_EN = 1'b0,
+    parameter PBUSER_W = 1
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_apb_if #(
+    .DATA_W(S_DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(S_STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) s_apb();
+
+taxi_apb_if #(
+    .DATA_W(M_DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(M_STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) m_apb();
+
+taxi_apb_adapter
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * APB slave interface
+     */
+    .s_apb(s_apb),
+
+    /*
+     * APB master interface
+     */
+    .m_apb(m_apb)
+);
+
+endmodule
+
+`resetall

src/apb/tb/taxi_apb_interconnect/Makefile

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_apb_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_M_CNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_PAUSER_EN := 0
+export PARAM_PAUSER_W := 1
+export PARAM_PWUSER_EN := 0
+export PARAM_PWUSER_W := 1
+export PARAM_PBUSER_EN := 0
+export PARAM_PBUSER_W := 1
+export PARAM_PRUSER_EN := 0
+export PARAM_PRUSER_W := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.py

@@ -0,0 +1,259 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb
+import cocotb_test.simulator
+import pytest
+from cocotb.clock import Clock
+from cocotb.regression import TestFactory
+from cocotb.triggers import RisingEdge, Timer
+from cocotbext.axi import ApbBus, ApbMaster, ApbRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
+        self.apb_ram = [
+            ApbRam(ApbBus.from_entity(ch), dut.clk, dut.rst, size=2**16)
+            for ch in dut.m_apb
+        ]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.apb_master.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for ram in self.apb_ram:
+                ram.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+):
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes * 2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset + 0x1000
+            addr = ram_addr + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram[m].write(ram_addr - 128, b"\xaa" * (length + 256))
+
+            await tb.apb_master.write(addr, test_data)
+
+            tb.log.debug(
+                "%s",
+                tb.apb_ram[m].hexdump_str(
+                    (ram_addr & ~0xF) - 16,
+                    (((ram_addr & 0xF) + length - 1) & ~0xF) + 48,
+                ),
+            )
+
+            assert tb.apb_ram[m].read(ram_addr, length) == test_data
+            assert tb.apb_ram[m].read(ram_addr - 1, 1) == b"\xaa"
+            assert tb.apb_ram[m].read(ram_addr + length, 1) == b"\xaa"
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+):
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes * 2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset + 0x1000
+            addr = ram_addr + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram[m].write(ram_addr, test_data)
+
+            data = await tb.apb_master.read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.apb_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset + random.randint(0, aperture - length) + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), "ns")
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), "ns")
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(
+            cocotb.start_soon(
+                worker(
+                    tb.apb_master,
+                    k * 0x1000,
+                    0x1000,
+                    count=16,
+                )
+            )
+        )
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, "top", None) is not None:
+    m_cnt = len(cocotb.top.m_apb)
+
+    for test in [run_test_write, run_test_read]:
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("m", range(min(m_cnt, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "rtl"))
+lib_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "lib"))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, "taxi", "src"))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == ".f":
+            with open(f, "r") as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_cnt", [1, 4])
+def test_taxi_apb_interconnect(request, m_cnt, data_w):
+    dut = "taxi_apb_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_apb_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters["M_CNT"] = m_cnt
+    parameters["DATA_W"] = data_w
+    parameters["ADDR_W"] = 32
+    parameters["STRB_W"] = parameters["DATA_W"] // 8
+    parameters["PAUSER_EN"] = 0
+    parameters["PAUSER_W"] = 1
+    parameters["PWUSER_EN"] = 0
+    parameters["PWUSER_W"] = 1
+    parameters["PRUSER_EN"] = 0
+    parameters["PRUSER_W"] = 1
+    parameters["PBUSER_EN"] = 0
+    parameters["PBUSER_W"] = 1
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.sv

@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB interconnect testbench
+ */
+module test_taxi_apb_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter M_CNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic PAUSER_EN = 1'b0,
+    parameter PAUSER_W = 1,
+    parameter logic PWUSER_EN = 1'b0,
+    parameter PWUSER_W = 1,
+    parameter logic PRUSER_EN = 1'b0,
+    parameter PRUSER_W = 1,
+    parameter logic PBUSER_EN = 1'b0,
+    parameter PBUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
+    parameter M_SECURE = {M_CNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_apb_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) s_apb(), m_apb[M_CNT]();
+
+taxi_apb_interconnect #(
+    .M_CNT(M_CNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * APB slave interface
+     */
+    .s_apb(s_apb),
+
+    /*
+     * APB master interface
+     */
+    .m_apb(m_apb)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar.f

@@ -0,0 +1,3 @@
+taxi_axi_crossbar.sv
+taxi_axi_crossbar_wr.f
+taxi_axi_crossbar_rd.f

src/axi/rtl/taxi_axi_crossbar.sv

@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar
+ */
+module taxi_axi_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT],
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+taxi_axi_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE (S_W_REG_TYPE),
+    .S_B_REG_TYPE (S_B_REG_TYPE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_wr(s_axi_wr),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_wr(m_axi_wr)
+);
+
+taxi_axi_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE (S_R_REG_TYPE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_rd(s_axi_rd),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_rd(m_axi_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_addr.sv

@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar address decode and admission control
+ */
+module taxi_axi_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Select signal width
+    parameter SEL_W = $clog2(M_COUNT),
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // ID field width
+    parameter ID_W = 8,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs
+    parameter S_THREADS = 32'd2,
+    // Number of concurrent operations
+    parameter S_ACCEPT = 32'd16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * Address input
+     */
+    input  wire logic [ID_W-1:0]    s_axi_aid,
+    input  wire logic [ADDR_W-1:0]  s_axi_aaddr,
+    input  wire logic [2:0]         s_axi_aprot,
+    input  wire logic [3:0]         s_axi_aqos,
+    input  wire logic               s_axi_avalid,
+    output wire logic               s_axi_aready,
+
+    /*
+     * Address output
+     */
+    output wire logic [3:0]         m_axi_aregion,
+    output wire logic [SEL_W-1:0]   m_select,
+    output wire logic               m_axi_avalid,
+    input  wire logic               m_axi_aready,
+
+    /*
+     * Write command output
+     */
+    output wire logic [SEL_W-1:0]   m_wc_select,
+    output wire logic               m_wc_decerr,
+    output wire logic               m_wc_valid,
+    input  wire logic               m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire logic               m_rc_decerr,
+    output wire logic               m_rc_valid,
+    input  wire logic               m_rc_ready,
+
+    /*
+     * Completion input
+     */
+    input  wire logic [ID_W-1:0]    s_cpl_id,
+    input  wire logic               s_cpl_valid
+);
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+localparam S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS;
+localparam CL_S_INT_THREADS = $clog2(S_INT_THREADS);
+localparam CL_S_ACCEPT = $clog2(S_ACCEPT);
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (M_REGIONS < 1 || M_REGIONS > 16)
+    $fatal(0, "Error: M_REGIONS must be between 1 and 16 (instance %m)");
+
+if (S_ACCEPT < 1)
+    $fatal(0, "Error: need at least 1 accept (instance %m)");
+
+if (S_THREADS < 1)
+    $fatal(0, "Error: need at least 1 thread (instance %m)");
+
+initial begin
+    if (S_THREADS > S_ACCEPT) begin
+        $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)");
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < 12 || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+    end
+
+    $display("Addressing configuration for axi_crossbar_addr instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [0:0]
+    STATE_IDLE = 1'd0,
+    STATE_DECODE = 1'd1;
+
+logic [0:0] state_reg = STATE_IDLE, state_next;
+
+logic s_axi_aready_reg = 1'b0, s_axi_aready_next;
+
+logic [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;
+logic [SEL_W-1:0] m_select_reg = '0, m_select_next;
+logic m_axi_avalid_reg = 1'b0, m_axi_avalid_next;
+logic m_decerr_reg = 1'b0, m_decerr_next;
+logic m_wc_valid_reg = 1'b0, m_wc_valid_next;
+logic m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axi_aready = s_axi_aready_reg;
+
+assign m_axi_aregion = m_axi_aregion_reg;
+assign m_select = m_select_reg;
+assign m_axi_avalid = m_axi_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+logic match;
+logic trans_start;
+logic trans_complete;
+
+localparam TR_CNT_W = $clog2(S_ACCEPT+1);
+logic [TR_CNT_W-1:0] trans_count_reg = 0;
+wire trans_limit = trans_count_reg >= TR_CNT_W'(S_ACCEPT) && !trans_complete;
+
+// transfer ID thread tracking
+logic [ID_W-1:0] thread_id_reg[S_INT_THREADS-1:0];
+logic [SEL_W-1:0] thread_m_reg[S_INT_THREADS-1:0];
+logic [3:0] thread_region_reg[S_INT_THREADS-1:0];
+logic [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0];
+
+// TODO fix loop
+/* verilator lint_off UNOPTFLAT */
+wire [S_INT_THREADS-1:0] thread_active;
+wire [S_INT_THREADS-1:0] thread_match;
+wire [S_INT_THREADS-1:0] thread_match_dest;
+wire [S_INT_THREADS-1:0] thread_cpl_match;
+wire [S_INT_THREADS-1:0] thread_trans_start;
+wire [S_INT_THREADS-1:0] thread_trans_complete;
+
+for (genvar n = 0; n < S_INT_THREADS; n = n + 1) begin
+    initial begin
+        thread_count_reg[n] = '0;
+    end
+
+    assign thread_active[n] = thread_count_reg[n] != 0;
+    assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid;
+    assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next);
+    assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id;
+    assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && thread_match == 0 && (thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))) == 0)) && trans_start;
+    assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (thread_trans_start[n]) begin
+            thread_id_reg[n] <= s_axi_aid;
+            thread_m_reg[n] <= m_select_next;
+            thread_region_reg[n] <= m_axi_aregion_next;
+        end
+
+        if (thread_trans_start[n] && !thread_trans_complete[n]) begin
+            thread_count_reg[n] <= thread_count_reg[n] + 1;
+        end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin
+            thread_count_reg[n] <= thread_count_reg[n] - 1;
+        end
+
+        if (rst) begin
+            thread_count_reg[n] <= 0;
+        end
+    end
+end
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+    trans_start = 1'b0;
+    trans_complete = 1'b0;
+
+    s_axi_aready_next = 1'b0;
+
+    m_axi_aregion_next = m_axi_aregion_reg;
+    m_select_next = m_select_reg;
+    m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axi_aready_next = 1'b0;
+
+            if (s_axi_avalid && !s_axi_aready) begin
+                match = 1'b0;
+                for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                    for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_axi_aprot[1]) && M_CONNECT_INT[i][S] && (s_axi_aaddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                            m_select_next = SEL_W'(i);
+                            m_axi_aregion_next = 4'(j);
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    if (!trans_limit && (thread_match_dest != 0 || (!(&thread_active) && thread_match == 0))) begin
+                        // transaction limit not reached
+                        m_axi_avalid_next = 1'b1;
+                        m_decerr_next = 1'b0;
+                        m_wc_valid_next = WC_OUTPUT;
+                        m_rc_valid_next = 1'b0;
+                        trans_start = 1'b1;
+                        state_next = STATE_DECODE;
+                    end else begin
+                        // transaction limit reached; block in idle
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    // decode error
+                    m_axi_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axi_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+
+    // manage completions
+    trans_complete = s_cpl_valid;
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+    s_axi_aready_reg <= s_axi_aready_next;
+    m_axi_avalid_reg <= m_axi_avalid_next;
+    m_wc_valid_reg <= m_wc_valid_next;
+    m_rc_valid_reg <= m_rc_valid_next;
+
+    if (trans_start && !trans_complete) begin
+        trans_count_reg <= trans_count_reg + 1;
+    end else if (!trans_start && trans_complete) begin
+        trans_count_reg <= trans_count_reg - 1;
+    end
+
+    m_axi_aregion_reg <= m_axi_aregion_next;
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_aready_reg <= 1'b0;
+        m_axi_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+
+        trans_count_reg <= 0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_rd.f

@@ -0,0 +1,6 @@
+taxi_axi_crossbar_rd.sv
+taxi_axi_crossbar_addr.sv
+taxi_axi_register_rd.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_crossbar_rd.sv

@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (read)
+ */
+module taxi_axi_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_rd[0].DATA_W;
+localparam S_ADDR_W = s_axi_rd[0].ADDR_W;
+localparam STRB_W = s_axi_rd[0].STRB_W;
+localparam S_ID_W = s_axi_rd[0].ID_W;
+localparam M_ID_W = m_axi_rd[0].ID_W;
+localparam logic ARUSER_EN = s_axi_rd[0].ARUSER_EN && m_axi_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
+localparam RUSER_W = s_axi_rd[0].RUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+localparam M_COUNT_P1 = M_COUNT+1;
+localparam CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+localparam [S_COUNT-1:0][31:0] S_THREADS_INT = S_THREADS;
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axi_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_ID_W < S_ID_W+$clog2(S_COUNT))
+    $fatal(0, "Error: M_ID_W must be at least $clog2(S_COUNT) larger than S_ID_W (instance %m)");
+
+wire [S_ID_W-1:0]    int_s_axi_arid[S_COUNT];
+wire [ADDR_W-1:0]    int_s_axi_araddr[S_COUNT];
+wire [7:0]           int_s_axi_arlen[S_COUNT];
+wire [2:0]           int_s_axi_arsize[S_COUNT];
+wire [1:0]           int_s_axi_arburst[S_COUNT];
+wire                 int_s_axi_arlock[S_COUNT];
+wire [3:0]           int_s_axi_arcache[S_COUNT];
+wire [2:0]           int_s_axi_arprot[S_COUNT];
+wire [3:0]           int_s_axi_arqos[S_COUNT];
+wire [3:0]           int_s_axi_arregion[S_COUNT];
+wire [ARUSER_W-1:0]  int_s_axi_aruser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_arvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_arready[M_COUNT];
+
+wire [M_ID_W-1:0]    int_m_axi_rid[M_COUNT];
+wire [DATA_W-1:0]    int_m_axi_rdata[M_COUNT];
+wire [1:0]           int_m_axi_rresp[M_COUNT];
+wire                 int_m_axi_rlast[M_COUNT];
+wire [RUSER_W-1:0]   int_m_axi_ruser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axi_rvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axi_rready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(s_axi_rd[0].DATA_W),
+        .ADDR_W(s_axi_rd[0].ADDR_W),
+        .STRB_W(s_axi_rd[0].STRB_W),
+        .ID_W(s_axi_rd[0].ID_W),
+        .ARUSER_EN(s_axi_rd[0].ARUSER_EN),
+        .ARUSER_W(s_axi_rd[0].ARUSER_W),
+        .RUSER_EN(s_axi_rd[0].RUSER_EN),
+        .RUSER_W(s_axi_rd[0].RUSER_W)
+    ) int_axi();
+
+    // S side register
+    taxi_axi_register_rd #(
+        .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+        .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_rd(s_axi_rd[m]),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_rd(int_axi)
+    );
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axi_avalid;
+    wire m_axi_aready;
+
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    wire [S_ID_W-1:0] s_cpl_id;
+    wire s_cpl_valid;
+
+    taxi_axi_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .ID_W(S_ID_W),
+        .S_THREADS(S_THREADS_INT[m]),
+        .S_ACCEPT(S_ACCEPT_INT[m]),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(0)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axi_aid(int_axi.arid),
+        .s_axi_aaddr(int_axi.araddr),
+        .s_axi_aprot(int_axi.arprot),
+        .s_axi_aqos(int_axi.arqos),
+        .s_axi_avalid(int_axi.arvalid),
+        .s_axi_aready(int_axi.arready),
+
+        /*
+         * Address output
+         */
+        .m_axi_aregion(int_s_axi_arregion[m]),
+        .m_select(a_select),
+        .m_axi_avalid(m_axi_avalid),
+        .m_axi_aready(m_axi_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(),
+        .m_wc_decerr(),
+        .m_wc_valid(),
+        .m_wc_ready(1'b1),
+
+        /*
+         * Response command output
+         */
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready),
+
+        /*
+         * Completion input
+         */
+        .s_cpl_id(s_cpl_id),
+        .s_cpl_valid(s_cpl_valid)
+    );
+
+    assign int_s_axi_arid[m] = int_axi.arid;
+    assign int_s_axi_araddr[m] = int_axi.araddr;
+    assign int_s_axi_arlen[m] = int_axi.arlen;
+    assign int_s_axi_arsize[m] = int_axi.arsize;
+    assign int_s_axi_arburst[m] = int_axi.arburst;
+    assign int_s_axi_arlock[m] = int_axi.arlock;
+    assign int_s_axi_arcache[m] = int_axi.arcache;
+    assign int_s_axi_arprot[m] = int_axi.arprot;
+    assign int_s_axi_arqos[m] = int_axi.arqos;
+    assign int_s_axi_aruser[m] = int_axi.aruser;
+
+    always_comb begin
+        int_axi_arvalid[m] = '0;
+        int_axi_arvalid[m][a_select] = m_axi_avalid;
+    end
+    assign m_axi_aready = int_axi_arready[a_select][m];
+
+    // decode error handling
+    logic [S_ID_W-1:0]  decerr_m_axi_rid_reg = '0, decerr_m_axi_rid_next;
+    logic               decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;
+    logic               decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;
+    wire                decerr_m_axi_rready;
+
+    logic [7:0] decerr_len_reg = 8'd0, decerr_len_next;
+
+    assign m_rc_ready = !decerr_m_axi_rvalid_reg;
+
+    always_comb begin
+        decerr_len_next = decerr_len_reg;
+        decerr_m_axi_rid_next = decerr_m_axi_rid_reg;
+        decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;
+        decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;
+
+        if (decerr_m_axi_rvalid_reg) begin
+            if (decerr_m_axi_rready) begin
+                if (decerr_len_reg != 0) begin
+                    decerr_len_next = decerr_len_reg-1;
+                    decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                    decerr_m_axi_rvalid_next = 1'b1;
+                end else begin
+                    decerr_m_axi_rvalid_next = 1'b0;
+                end
+            end
+        end else if (m_rc_valid && m_rc_ready) begin
+            decerr_len_next = int_axi.arlen;
+            decerr_m_axi_rid_next = int_axi.arid;
+            decerr_m_axi_rlast_next = (decerr_len_next == 0);
+            decerr_m_axi_rvalid_next = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;
+        decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;
+        decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;
+        decerr_len_reg <= decerr_len_next;
+
+        if (rst) begin
+            decerr_m_axi_rvalid_reg <= 1'b0;
+        end
+    end
+
+    // read response arbitration
+    wire [M_COUNT_P1-1:0] r_req;
+    wire [M_COUNT_P1-1:0] r_ack;
+    wire [M_COUNT_P1-1:0] r_grant;
+    wire r_grant_valid;
+    wire [CL_M_COUNT_P1-1:0] r_grant_index;
+
+    taxi_arbiter #(
+        .PORTS(M_COUNT_P1),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    r_arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(r_req),
+        .ack(r_ack),
+        .grant(r_grant),
+        .grant_valid(r_grant_valid),
+        .grant_index(r_grant_index)
+    );
+
+    // read response mux
+    always_comb begin
+        if (r_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1)) begin
+            int_axi.rid    = decerr_m_axi_rid_reg;
+            int_axi.rdata  = '0;
+            int_axi.rresp  = 2'b11;
+            int_axi.rlast  = decerr_m_axi_rlast_reg;
+            int_axi.ruser  = '0;
+            int_axi.rvalid = decerr_m_axi_rvalid_reg & r_grant_valid;
+        end else begin
+            int_axi.rid    = S_ID_W'(int_m_axi_rid[r_grant_index[CL_M_COUNT_INT-1:0]]);
+            int_axi.rdata  = int_m_axi_rdata[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rresp  = int_m_axi_rresp[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rlast  = int_m_axi_rlast[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.ruser  = int_m_axi_ruser[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rvalid = int_axi_rvalid[r_grant_index[CL_M_COUNT_INT-1:0]][m] & r_grant_valid;
+        end
+    end
+
+    always_comb begin
+        int_axi_rready[m] = '0;
+        int_axi_rready[m][r_grant_index[CL_M_COUNT_INT-1:0]] = r_grant_valid && int_axi.rready;
+    end
+
+    assign decerr_m_axi_rready = (r_grant_valid && int_axi.rready) && (r_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1));
+
+    for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+        assign r_req[n] = int_axi_rvalid[n][m] && !r_grant[n];
+        assign r_ack[n] = r_grant_valid && int_axi_rvalid[n][m] && int_axi.rlast && int_axi.rready;
+    end
+
+    assign r_req[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];
+    assign r_ack[M_COUNT_P1-1] = r_grant_valid && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && int_axi.rready;
+
+    assign s_cpl_id = int_axi.rid;
+    assign s_cpl_valid = int_axi.rvalid && int_axi.rready && int_axi.rlast;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(m_axi_rd[0].DATA_W),
+        .ADDR_W(m_axi_rd[0].ADDR_W),
+        .STRB_W(m_axi_rd[0].STRB_W),
+        .ID_W(m_axi_rd[0].ID_W),
+        .ARUSER_EN(m_axi_rd[0].ARUSER_EN),
+        .ARUSER_W(m_axi_rd[0].ARUSER_W),
+        .RUSER_EN(m_axi_rd[0].RUSER_EN),
+        .RUSER_W(m_axi_rd[0].RUSER_W)
+    ) int_axi();
+
+    // in-flight transaction count
+    wire trans_start;
+    wire trans_complete;
+    localparam TR_CNT_W = $clog2(M_ISSUE_INT[n]+1);
+    logic [TR_CNT_W-1:0] trans_count_reg = '0;
+
+    wire trans_limit = trans_count_reg >= TR_CNT_W'(M_ISSUE_INT[n]) && !trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            trans_count_reg <= 0;
+        end else begin
+            if (trans_start && !trans_complete) begin
+                trans_count_reg <= trans_count_reg + 1;
+            end else if (!trans_start && trans_complete) begin
+                trans_count_reg <= trans_count_reg - 1;
+            end
+        end
+    end
+
+    // address arbitration
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    if (S_COUNT > 1) begin
+        assign int_axi.arid = {a_grant_index, int_s_axi_arid[a_grant_index]};
+    end else begin
+        assign int_axi.arid = int_s_axi_arid[a_grant_index];
+    end
+    assign int_axi.araddr   = AXI_M_ADDR_W'(int_s_axi_araddr[a_grant_index]);
+    assign int_axi.arlen    = int_s_axi_arlen[a_grant_index];
+    assign int_axi.arsize   = int_s_axi_arsize[a_grant_index];
+    assign int_axi.arburst  = int_s_axi_arburst[a_grant_index];
+    assign int_axi.arlock   = int_s_axi_arlock[a_grant_index];
+    assign int_axi.arcache  = int_s_axi_arcache[a_grant_index];
+    assign int_axi.arprot   = int_s_axi_arprot[a_grant_index];
+    assign int_axi.arqos    = int_s_axi_arqos[a_grant_index];
+    assign int_axi.arregion = int_s_axi_arregion[a_grant_index];
+    assign int_axi.aruser   = int_s_axi_aruser[a_grant_index];
+    assign int_axi.arvalid  = int_axi_arvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axi_arready[n] = '0;
+        int_axi_arready[n][a_grant_index] = a_grant_valid && int_axi.arready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axi_arvalid[m][n] && !a_grant_valid && !trans_limit;
+        assign a_ack[m] = a_grant[m] && int_axi_arvalid[m][n] && int_axi.arready;
+    end
+
+    assign trans_start = int_axi.arvalid && int_axi.arready && a_grant_valid;
+
+    // read response forwarding
+    wire [CL_S_COUNT_INT-1:0] r_select = CL_S_COUNT_INT'(int_axi.rid >> S_ID_W);
+
+    assign int_m_axi_rid[n]   = int_axi.rid;
+    assign int_m_axi_rdata[n] = int_axi.rdata;
+    assign int_m_axi_rresp[n] = int_axi.rresp;
+    assign int_m_axi_rlast[n] = int_axi.rlast;
+    assign int_m_axi_ruser[n] = int_axi.ruser;
+
+    always_comb begin
+        int_axi_rvalid[n] = '0;
+        int_axi_rvalid[n][r_select] = int_axi.rvalid;
+    end
+    assign int_axi.rready = int_axi_rready[r_select][n];
+
+    assign trans_complete = int_axi.rvalid && int_axi.rready && int_axi.rlast;
+
+    // M side register
+    taxi_axi_register_rd #(
+        .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+        .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_rd(int_axi),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_rd(m_axi_rd[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_wr.f

@@ -0,0 +1,6 @@
+taxi_axi_crossbar_wr.sv
+taxi_axi_crossbar_addr.sv
+taxi_axi_register_wr.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_crossbar_wr.sv

@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (write)
+ */
+module taxi_axi_crossbar_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_wr[0].DATA_W;
+localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
+localparam STRB_W = s_axi_wr[0].STRB_W;
+localparam S_ID_W = s_axi_wr[0].ID_W;
+localparam M_ID_W = m_axi_wr[0].ID_W;
+localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
+localparam WUSER_W = s_axi_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
+localparam BUSER_W = s_axi_wr[0].BUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+localparam M_COUNT_P1 = M_COUNT+1;
+localparam CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+localparam [S_COUNT-1:0][31:0] S_THREADS_INT = S_THREADS;
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axi_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_ID_W < S_ID_W+$clog2(S_COUNT))
+    $fatal(0, "Error: M_ID_W must be at least $clog2(S_COUNT) larger than S_ID_W (instance %m)");
+
+wire [S_ID_W-1:0]    int_s_axi_awid[S_COUNT];
+wire [ADDR_W-1:0]    int_s_axi_awaddr[S_COUNT];
+wire [7:0]           int_s_axi_awlen[S_COUNT];
+wire [2:0]           int_s_axi_awsize[S_COUNT];
+wire [1:0]           int_s_axi_awburst[S_COUNT];
+wire                 int_s_axi_awlock[S_COUNT];
+wire [3:0]           int_s_axi_awcache[S_COUNT];
+wire [2:0]           int_s_axi_awprot[S_COUNT];
+wire [3:0]           int_s_axi_awqos[S_COUNT];
+wire [3:0]           int_s_axi_awregion[S_COUNT];
+wire [AWUSER_W-1:0]  int_s_axi_awuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_awvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_awready[M_COUNT];
+
+wire [DATA_W-1:0]    int_s_axi_wdata[S_COUNT];
+wire [STRB_W-1:0]    int_s_axi_wstrb[S_COUNT];
+wire                 int_s_axi_wlast[S_COUNT];
+wire [WUSER_W-1:0]   int_s_axi_wuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_wvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_wready[M_COUNT];
+
+wire [M_ID_W-1:0]    int_m_axi_bid[M_COUNT];
+wire [1:0]           int_m_axi_bresp[M_COUNT];
+wire [BUSER_W-1:0]   int_m_axi_buser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axi_bvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axi_bready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(s_axi_wr[0].DATA_W),
+        .ADDR_W(s_axi_wr[0].ADDR_W),
+        .STRB_W(s_axi_wr[0].STRB_W),
+        .ID_W(s_axi_wr[0].ID_W),
+        .AWUSER_EN(s_axi_wr[0].AWUSER_EN),
+        .AWUSER_W(s_axi_wr[0].AWUSER_W),
+        .WUSER_EN(s_axi_wr[0].WUSER_EN),
+        .WUSER_W(s_axi_wr[0].WUSER_W),
+        .BUSER_EN(s_axi_wr[0].BUSER_EN),
+        .BUSER_W(s_axi_wr[0].BUSER_W)
+    ) int_axi();
+
+    // S side register
+    taxi_axi_register_wr #(
+        .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+        .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+        .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_wr(s_axi_wr[m]),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_wr(int_axi)
+    );
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axi_avalid;
+    wire m_axi_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_wc_select;
+    wire m_wc_decerr;
+    wire m_wc_valid;
+    wire m_wc_ready;
+
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    wire [S_ID_W-1:0] s_cpl_id;
+    wire s_cpl_valid;
+
+    taxi_axi_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .ID_W(S_ID_W),
+        .S_THREADS(S_THREADS_INT[m]),
+        .S_ACCEPT(S_ACCEPT_INT[m]),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(1)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axi_aid(int_axi.awid),
+        .s_axi_aaddr(int_axi.awaddr),
+        .s_axi_aprot(int_axi.awprot),
+        .s_axi_aqos(int_axi.awqos),
+        .s_axi_avalid(int_axi.awvalid),
+        .s_axi_aready(int_axi.awready),
+
+        /*
+         * Address output
+         */
+        .m_axi_aregion(int_s_axi_awregion[m]),
+        .m_select(a_select),
+        .m_axi_avalid(m_axi_avalid),
+        .m_axi_aready(m_axi_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(m_wc_select),
+        .m_wc_decerr(m_wc_decerr),
+        .m_wc_valid(m_wc_valid),
+        .m_wc_ready(m_wc_ready),
+
+        /*
+         * Response command output
+         */
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready),
+
+        /*
+         * Completion input
+         */
+        .s_cpl_id(s_cpl_id),
+        .s_cpl_valid(s_cpl_valid)
+    );
+
+    assign int_s_axi_awid[m] = int_axi.awid;
+    assign int_s_axi_awaddr[m] = int_axi.awaddr;
+    assign int_s_axi_awlen[m] = int_axi.awlen;
+    assign int_s_axi_awsize[m] = int_axi.awsize;
+    assign int_s_axi_awburst[m] = int_axi.awburst;
+    assign int_s_axi_awlock[m] = int_axi.awlock;
+    assign int_s_axi_awcache[m] = int_axi.awcache;
+    assign int_s_axi_awprot[m] = int_axi.awprot;
+    assign int_s_axi_awqos[m] = int_axi.awqos;
+    assign int_s_axi_awuser[m] = int_axi.awuser;
+
+    always_comb begin
+        int_axi_awvalid[m] = '0;
+        int_axi_awvalid[m][a_select] = m_axi_avalid;
+    end
+    assign m_axi_aready = int_axi_awready[a_select][m];
+
+    // write command handling
+    logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_drop_reg = 1'b0, w_drop_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+
+    assign m_wc_ready = !w_select_valid_reg;
+
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_drop_next = w_drop_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+        w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+
+        if (m_wc_valid && !w_select_valid_reg) begin
+            w_select_next = m_wc_select;
+            w_drop_next = m_wc_decerr;
+            w_select_valid_next = m_wc_valid;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_reg <= w_select_next;
+        w_drop_reg <= w_drop_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+        end
+    end
+
+    // write data forwarding
+    assign int_s_axi_wdata[m] = int_axi.wdata;
+    assign int_s_axi_wstrb[m] = int_axi.wstrb;
+    assign int_s_axi_wlast[m] = int_axi.wlast;
+    assign int_s_axi_wuser[m] = int_axi.wuser;
+
+    always_comb begin
+        int_axi_wvalid[m] = '0;
+        int_axi_wvalid[m][w_select_reg] = int_axi.wvalid && w_select_valid_reg && !w_drop_reg;
+    end
+    assign int_axi.wready = int_axi_wready[w_select_reg][m] || w_drop_reg;
+
+    // decode error handling
+    logic [S_ID_W-1:0]  decerr_m_axi_bid_reg = '0, decerr_m_axi_bid_next;
+    logic               decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;
+    wire                decerr_m_axi_bready;
+
+    assign m_rc_ready = !decerr_m_axi_bvalid_reg;
+
+    always_comb begin
+        decerr_m_axi_bid_next = decerr_m_axi_bid_reg;
+        decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;
+
+        if (decerr_m_axi_bvalid_reg) begin
+            if (decerr_m_axi_bready) begin
+                decerr_m_axi_bvalid_next = 1'b0;
+            end
+        end else if (m_rc_valid && m_rc_ready) begin
+            decerr_m_axi_bid_next = int_s_axi_awid[m];
+            decerr_m_axi_bvalid_next = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            decerr_m_axi_bvalid_reg <= 1'b0;
+        end else begin
+            decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;
+        end
+
+        decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;
+    end
+
+    // write response arbitration
+    wire [M_COUNT_P1-1:0] b_req;
+    wire [M_COUNT_P1-1:0] b_ack;
+    wire [M_COUNT_P1-1:0] b_grant;
+    wire b_grant_valid;
+    wire [CL_M_COUNT_P1-1:0] b_grant_index;
+
+    taxi_arbiter #(
+        .PORTS(M_COUNT_P1),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    b_arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(b_req),
+        .ack(b_ack),
+        .grant(b_grant),
+        .grant_valid(b_grant_valid),
+        .grant_index(b_grant_index)
+    );
+
+    // write response mux
+    always_comb begin
+        if (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1)) begin
+            int_axi.bid    = decerr_m_axi_bid_reg;
+            int_axi.bresp  = 2'b11;
+            int_axi.buser  = '0;
+            int_axi.bvalid = decerr_m_axi_bvalid_reg & b_grant_valid;
+        end else begin
+            int_axi.bid    = S_ID_W'(int_m_axi_bid[b_grant_index[CL_M_COUNT_INT-1:0]]);
+            int_axi.bresp  = int_m_axi_bresp[b_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.buser  = int_m_axi_buser[b_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.bvalid = int_axi_bvalid[b_grant_index[CL_M_COUNT_INT-1:0]][m] & b_grant_valid;
+        end
+    end
+
+    always_comb begin
+        int_axi_bready[m] = '0;
+        int_axi_bready[m][b_grant_index[CL_M_COUNT_INT-1:0]] = b_grant_valid && int_axi.bready;
+    end
+
+    assign decerr_m_axi_bready = (b_grant_valid && int_axi.bready) && (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1));
+
+    for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+        assign b_req[n] = int_axi_bvalid[n][m] && !b_grant[n];
+        assign b_ack[n] = b_grant[n] && int_axi_bvalid[n][m] && int_axi.bready;
+    end
+
+    assign b_req[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
+    assign b_ack[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && int_axi.bready;
+
+    assign s_cpl_id = int_axi.bid;
+    assign s_cpl_valid = int_axi.bvalid && int_axi.bready;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(m_axi_wr[0].DATA_W),
+        .ADDR_W(m_axi_wr[0].ADDR_W),
+        .STRB_W(m_axi_wr[0].STRB_W),
+        .ID_W(m_axi_wr[0].ID_W),
+        .AWUSER_EN(m_axi_wr[0].AWUSER_EN),
+        .AWUSER_W(m_axi_wr[0].AWUSER_W),
+        .WUSER_EN(m_axi_wr[0].WUSER_EN),
+        .WUSER_W(m_axi_wr[0].WUSER_W),
+        .BUSER_EN(m_axi_wr[0].BUSER_EN),
+        .BUSER_W(m_axi_wr[0].BUSER_W)
+    ) int_axi();
+
+    // in-flight transaction count
+    wire trans_start;
+    wire trans_complete;
+    localparam TR_CNT_W = $clog2(M_ISSUE_INT[n]+1);
+    logic [TR_CNT_W-1:0] trans_count_reg = '0;
+
+    wire trans_limit = trans_count_reg >= TR_CNT_W'(M_ISSUE_INT[n]) && !trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (trans_start && !trans_complete) begin
+            trans_count_reg <= trans_count_reg + 1;
+        end else if (!trans_start && trans_complete) begin
+            trans_count_reg <= trans_count_reg - 1;
+        end
+
+        if (rst) begin
+            trans_count_reg <= 0;
+        end
+    end
+
+    // address arbitration
+    logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+    logic w_select_new_reg = 1'b0, w_select_new_next;
+
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    if (S_COUNT > 1) begin
+        assign int_axi.awid = {a_grant_index, int_s_axi_awid[a_grant_index]};
+    end else begin
+        assign int_axi.awid = int_s_axi_awid[a_grant_index];
+    end
+    assign int_axi.awaddr   = AXI_M_ADDR_W'(int_s_axi_awaddr[a_grant_index]);
+    assign int_axi.awlen    = int_s_axi_awlen[a_grant_index];
+    assign int_axi.awsize   = int_s_axi_awsize[a_grant_index];
+    assign int_axi.awburst  = int_s_axi_awburst[a_grant_index];
+    assign int_axi.awlock   = int_s_axi_awlock[a_grant_index];
+    assign int_axi.awcache  = int_s_axi_awcache[a_grant_index];
+    assign int_axi.awprot   = int_s_axi_awprot[a_grant_index];
+    assign int_axi.awqos    = int_s_axi_awqos[a_grant_index];
+    assign int_axi.awregion = int_s_axi_awregion[a_grant_index];
+    assign int_axi.awuser   = int_s_axi_awuser[a_grant_index];
+    assign int_axi.awvalid  = int_axi_awvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axi_awready[n] = '0;
+        int_axi_awready[n][a_grant_index] = a_grant_valid && int_axi.awready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axi_awvalid[m][n] && !a_grant_valid && !trans_limit && !w_select_valid_next;
+        assign a_ack[m] = a_grant[m] && int_axi_awvalid[m][n] && int_axi.awready;
+    end
+
+    assign trans_start = int_axi.awvalid && int_axi.awready && a_grant_valid;
+
+    // write data mux
+    assign int_axi.wdata   = int_s_axi_wdata[w_select_reg];
+    assign int_axi.wstrb   = int_s_axi_wstrb[w_select_reg];
+    assign int_axi.wlast   = int_s_axi_wlast[w_select_reg];
+    assign int_axi.wuser   = int_s_axi_wuser[w_select_reg];
+    assign int_axi.wvalid  = int_axi_wvalid[w_select_reg][n] && w_select_valid_reg;
+
+    always_comb begin
+        int_axi_wready[n] = '0;
+        int_axi_wready[n][w_select_reg] = w_select_valid_reg && int_axi.wready;
+    end
+
+    // write data routing
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+        w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0;
+
+        if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+            w_select_next = a_grant_index;
+            w_select_valid_next = a_grant_valid;
+            w_select_new_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_reg <= w_select_next;
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_new_reg <= w_select_new_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+            w_select_new_reg <= 1'b1;
+        end
+    end
+
+    // write response forwarding
+    wire [CL_S_COUNT_INT-1:0] b_select = CL_S_COUNT_INT'(int_axi.bid >> S_ID_W);
+
+    assign int_m_axi_bid[n] = int_axi.bid;
+    assign int_m_axi_bresp[n] = int_axi.bresp;
+    assign int_m_axi_buser[n] = int_axi.buser;
+
+    always_comb begin
+        int_axi_bvalid[n] = '0;
+        int_axi_bvalid[n][b_select] = int_axi.bvalid;
+    end
+    assign int_axi.bready = int_axi_bready[b_select][n];
+
+    assign trans_complete = int_axi.bvalid && int_axi.bready;
+
+    // M side register
+    taxi_axi_register_wr #(
+        .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+        .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+        .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_wr(int_axi),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_wr(m_axi_wr[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_fifo_rd.sv

@@ -61,20 +61,20 @@ if (m_axi_rd.DATA_W != DATA_W)
 if (m_axi_rd.STRB_W != STRB_W)
     $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
 
-reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
-reg [FIFO_AW:0] wr_addr_reg = '0;
-reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
-reg [FIFO_AW:0] rd_addr_reg = '0;
+logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
+logic [FIFO_AW:0] wr_addr_reg = '0;
+logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
+logic [FIFO_AW:0] rd_addr_reg = '0;
 
 (* ramstyle = "no_rw_check" *)
-reg [RWIDTH-1:0] mem[2**FIFO_AW];
-reg [RWIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+logic [RWIDTH-1:0] mem[2**FIFO_AW];
+logic [RWIDTH-1:0] mem_read_data_reg;
+logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
 
 wire [RWIDTH-1:0] m_axi_r;
 
-reg [RWIDTH-1:0] s_axi_r_reg;
-reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+logic [RWIDTH-1:0] s_axi_r_reg;
+logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
 
 // full when first MSB different but rest same
 wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -83,9 +83,9 @@ wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
 wire empty = wr_ptr_reg == rd_ptr_reg;
 
 // control signals
-reg write;
-reg read;
-reg store_output;
+logic write;
+logic read;
+logic store_output;
 
 assign m_axi_rd.rready = !full;
 
@@ -104,24 +104,24 @@ if (FIFO_DELAY) begin
         STATE_IDLE = 1'd0,
         STATE_WAIT = 1'd1;
 
-    reg [0:0] state_reg = STATE_IDLE, state_next;
+    logic [0:0] state_reg = STATE_IDLE, state_next;
 
-    reg [COUNT_W-1:0] count_reg = 0, count_next;
+    logic [COUNT_W-1:0] count_reg = 0, count_next;
 
-    reg [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next;
-    reg [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next;
-    reg [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next;
-    reg [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next;
-    reg [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next;
-    reg m_axi_arlock_reg = '0, m_axi_arlock_next;
-    reg [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next;
-    reg [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next;
-    reg [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next;
-    reg [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next;
-    reg [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next;
-    reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
+    logic [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next;
+    logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next;
+    logic [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next;
+    logic [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next;
+    logic [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next;
+    logic m_axi_arlock_reg = '0, m_axi_arlock_next;
+    logic [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next;
+    logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next;
+    logic [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next;
+    logic [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next;
+    logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next;
+    logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
 
-    reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+    logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
 
     assign m_axi_rd.arid = m_axi_arid_reg;
     assign m_axi_rd.araddr = m_axi_araddr_reg;

src/axi/rtl/taxi_axi_fifo_wr.sv

@@ -62,20 +62,20 @@ if (m_axi_wr.DATA_W != DATA_W)
 if (m_axi_wr.STRB_W != STRB_W)
     $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
 
-reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
-reg [FIFO_AW:0] wr_addr_reg = '0;
-reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
-reg [FIFO_AW:0] rd_addr_reg = '0;
+logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
+logic [FIFO_AW:0] wr_addr_reg = '0;
+logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
+logic [FIFO_AW:0] rd_addr_reg = '0;
 
 (* ramstyle = "no_rw_check" *)
-reg [WWIDTH-1:0] mem[2**FIFO_AW];
-reg [WWIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+logic [WWIDTH-1:0] mem[2**FIFO_AW];
+logic [WWIDTH-1:0] mem_read_data_reg;
+logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
 
 wire [WWIDTH-1:0] s_axi_w;
 
-reg [WWIDTH-1:0] m_axi_w_reg;
-reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+logic [WWIDTH-1:0] m_axi_w_reg;
+logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
 
 // full when first MSB different but rest same
 wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -86,9 +86,9 @@ wire empty = wr_ptr_reg == rd_ptr_reg;
 wire hold;
 
 // control signals
-reg write;
-reg read;
-reg store_output;
+logic write;
+logic read;
+logic store_output;
 
 assign s_axi_wr.wready = !full && !hold;
 assign s_axi_w[DATA_W-1:0] = s_axi_wr.wdata;
@@ -104,25 +104,25 @@ if (FIFO_DELAY) begin
         STATE_TRANSFER_IN = 2'd1,
         STATE_TRANSFER_OUT = 2'd2;
 
-    reg [1:0] state_reg = STATE_IDLE, state_next;
+    logic [1:0] state_reg = STATE_IDLE, state_next;
 
-    reg hold_reg = 1'b1, hold_next;
-    reg [8:0] count_reg = 9'd0, count_next;
+    logic hold_reg = 1'b1, hold_next;
+    logic [8:0] count_reg = 9'd0, count_next;
 
-    reg [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next;
-    reg [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
-    reg [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next;
-    reg [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next;
-    reg [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next;
-    reg m_axi_awlock_reg = '0, m_axi_awlock_next;
-    reg [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next;
-    reg [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
-    reg [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next;
-    reg [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next;
-    reg [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
-    reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
+    logic [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next;
+    logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
+    logic [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next;
+    logic [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next;
+    logic [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next;
+    logic m_axi_awlock_reg = '0, m_axi_awlock_next;
+    logic [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next;
+    logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
+    logic [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next;
+    logic [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next;
+    logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
+    logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
 
-    reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+    logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
 
     assign m_axi_wr.awid = m_axi_awid_reg;
     assign m_axi_wr.awaddr = m_axi_awaddr_reg;

src/axi/rtl/taxi_axi_interconnect.f

@@ -0,0 +1,6 @@
+taxi_axi_interconnect.sv
+taxi_axi_interconnect_rd.sv
+taxi_axi_interconnect_wr.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_interconnect.sv

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT],
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+taxi_axi_interconnect_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interfaces
+     */
+    .s_axi_wr(s_axi_wr),
+
+    /*
+     * AXI4 master interfaces
+     */
+    .m_axi_wr(m_axi_wr)
+);
+
+taxi_axi_interconnect_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_SECURE(M_SECURE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interfaces
+     */
+    .s_axi_rd(s_axi_rd),
+
+    /*
+     * AXI4 master interfaces
+     */
+    .m_axi_rd(m_axi_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_interconnect_rd.sv

@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_rd[0].DATA_W;
+localparam S_ADDR_W = s_axi_rd[0].ADDR_W;
+localparam STRB_W = s_axi_rd[0].STRB_W;
+localparam S_ID_W = s_axi_rd[0].ID_W;
+localparam M_ID_W = m_axi_rd.ID_W;
+localparam logic ARUSER_EN = s_axi_rd[0].ARUSER_EN && m_axi_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
+localparam RUSER_W = s_axi_rd[0].RUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axi_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_REGIONS < 1 || M_REGIONS > 16)
+    $fatal(0, "Error: M_REGIONS must be between 1 and 16 (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axi_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_READ = 3'd2,
+    STATE_READ_DROP = 3'd3,
+    STATE_WAIT_IDLE = 3'd4;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next;
+logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next;
+logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
+logic [7:0] axi_len_reg = 8'd0, axi_len_next;
+logic [2:0] axi_size_reg = 3'd0, axi_size_next;
+logic [1:0] axi_burst_reg = 2'd0, axi_burst_next;
+logic axi_lock_reg = 1'b0, axi_lock_next;
+logic [3:0] axi_cache_reg = 4'd0, axi_cache_next;
+logic [2:0] axi_prot_reg = 3'b000, axi_prot_next;
+logic [3:0] axi_qos_reg = 4'd0, axi_qos_next;
+logic [3:0] axi_region_reg = 4'd0, axi_region_next;
+logic [ARUSER_W-1:0] axi_aruser_reg = '0, axi_aruser_next;
+
+logic [S_COUNT-1:0] s_axi_arready_reg = '0, s_axi_arready_next;
+
+logic [M_COUNT-1:0] m_axi_arvalid_reg = '0, m_axi_arvalid_next;
+logic [M_COUNT-1:0] m_axi_rready_reg = '0, m_axi_rready_next;
+
+// internal datapath
+logic  [S_ID_W-1:0]   s_axi_rid_int;
+logic  [DATA_W-1:0]   s_axi_rdata_int;
+logic  [1:0]          s_axi_rresp_int;
+logic                 s_axi_rlast_int;
+logic  [RUSER_W-1:0]  s_axi_ruser_int;
+logic  [S_COUNT-1:0]  s_axi_rvalid_int;
+logic                 s_axi_rready_int_reg = 1'b0;
+wire                  s_axi_rready_int_early;
+
+// unpack interface array
+wire [S_ID_W-1:0]    s_axi_arid[S_COUNT];
+wire [ADDR_W-1:0]    s_axi_araddr[S_COUNT];
+wire [7:0]           s_axi_arlen[S_COUNT];
+wire [2:0]           s_axi_arsize[S_COUNT];
+wire [1:0]           s_axi_arburst[S_COUNT];
+wire                 s_axi_arlock[S_COUNT];
+wire [3:0]           s_axi_arcache[S_COUNT];
+wire [2:0]           s_axi_prot[S_COUNT];
+wire [3:0]           s_axi_arqos[S_COUNT];
+wire [ARUSER_W-1:0]  s_axi_aruser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_arvalid;
+
+wire [M_COUNT-1:0]   m_axi_arready;
+wire [M_ID_W-1:0]    m_axi_rid[M_COUNT];
+wire [DATA_W-1:0]    m_axi_rdata[M_COUNT];
+wire [1:0]           m_axi_rresp[M_COUNT];
+wire                 m_axi_rlast[M_COUNT];
+wire [RUSER_W-1:0]   m_axi_ruser[M_COUNT];
+wire [M_COUNT-1:0]   m_axi_rvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_arid[n] = s_axi_rd[n].arid;
+    assign s_axi_araddr[n] = s_axi_rd[n].araddr;
+    assign s_axi_arlen[n] = s_axi_rd[n].arlen;
+    assign s_axi_arsize[n] = s_axi_rd[n].arsize;
+    assign s_axi_arburst[n] = s_axi_rd[n].arburst;
+    assign s_axi_arlock[n] = s_axi_rd[n].arlock;
+    assign s_axi_arcache[n] = s_axi_rd[n].arcache;
+    assign s_axi_prot[n] = s_axi_rd[n].arprot;
+    assign s_axi_arqos[n] = s_axi_rd[n].arqos;
+    assign s_axi_aruser[n] = s_axi_rd[n].aruser;
+    assign s_axi_arvalid[n] = s_axi_rd[n].arvalid;
+    assign s_axi_rd[n].arready = s_axi_arready_reg[n];
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_rd[n].arid = axi_id_reg;
+    assign m_axi_rd[n].araddr = AXI_M_ADDR_W'(axi_addr_reg);
+    assign m_axi_rd[n].arlen = axi_len_reg;
+    assign m_axi_rd[n].arsize = axi_size_reg;
+    assign m_axi_rd[n].arburst = axi_burst_reg;
+    assign m_axi_rd[n].arlock = axi_lock_reg;
+    assign m_axi_rd[n].arcache = axi_cache_reg;
+    assign m_axi_rd[n].arprot = axi_prot_reg;
+    assign m_axi_rd[n].arqos = axi_qos_reg;
+    assign m_axi_rd[n].aruser = ARUSER_EN ? axi_aruser_reg : '0;
+    assign m_axi_rd[n].arvalid = m_axi_arvalid_reg[n];
+    assign m_axi_arready[n] = m_axi_rd[n].arready;
+    assign m_axi_rid[n] = m_axi_rd[n].rid;
+    assign m_axi_rdata[n] = m_axi_rd[n].rdata;
+    assign m_axi_rresp[n] = m_axi_rd[n].rresp;
+    assign m_axi_rlast[n] = m_axi_rd[n].rlast;
+    assign m_axi_ruser[n] = m_axi_rd[n].ruser;
+    assign m_axi_rvalid[n] = m_axi_rd[n].rvalid;
+    assign m_axi_rd[n].rready = m_axi_rready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [S_ID_W-1:0]    current_s_axi_arid    = s_axi_arid[s_select];
+wire [ADDR_W-1:0]    current_s_axi_araddr  = s_axi_araddr[s_select];
+wire [7:0]           current_s_axi_arlen   = s_axi_arlen[s_select];
+wire [2:0]           current_s_axi_arsize  = s_axi_arsize[s_select];
+wire [1:0]           current_s_axi_arburst = s_axi_arburst[s_select];
+wire                 current_s_axi_arlock  = s_axi_arlock[s_select];
+wire [3:0]           current_s_axi_arcache = s_axi_arcache[s_select];
+wire [2:0]           current_s_axi_prot    = s_axi_prot[s_select];
+wire [3:0]           current_s_axi_arqos   = s_axi_arqos[s_select];
+wire [ARUSER_W-1:0]  current_s_axi_aruser  = s_axi_aruser[s_select];
+wire                 current_s_axi_arvalid = s_axi_arvalid[s_select];
+wire                 current_s_axi_rready  = s_axi_rready[s_select];
+
+// master side mux
+wire                 current_m_axi_arready = m_axi_arready[m_select_reg];
+wire [M_ID_W-1:0]    current_m_axi_rid     = m_axi_rid[m_select_reg];
+wire [DATA_W-1:0]    current_m_axi_rdata   = m_axi_rdata[m_select_reg];
+wire [1:0]           current_m_axi_rresp   = m_axi_rresp[m_select_reg];
+wire                 current_m_axi_rlast   = m_axi_rlast[m_select_reg];
+wire [RUSER_W-1:0]   current_m_axi_ruser   = m_axi_ruser[m_select_reg];
+wire                 current_m_axi_rvalid  = m_axi_rvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+// req generation
+assign req = s_axi_arvalid;
+assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axi_id_next = axi_id_reg;
+    axi_addr_next = axi_addr_reg;
+    axi_addr_valid_next = axi_addr_valid_reg;
+    axi_len_next = axi_len_reg;
+    axi_size_next = axi_size_reg;
+    axi_burst_next = axi_burst_reg;
+    axi_lock_next = axi_lock_reg;
+    axi_cache_next = axi_cache_reg;
+    axi_prot_next = axi_prot_reg;
+    axi_qos_next = axi_qos_reg;
+    axi_region_next = axi_region_reg;
+    axi_aruser_next = axi_aruser_reg;
+
+    s_axi_arready_next = '0;
+
+    m_axi_arvalid_next = m_axi_arvalid_reg & ~m_axi_arready;
+    m_axi_rready_next = '0;
+
+    s_axi_rid_int = axi_id_reg;
+    s_axi_rdata_int = current_m_axi_rdata;
+    s_axi_rresp_int = current_m_axi_rresp;
+    s_axi_rlast_int = current_m_axi_rlast;
+    s_axi_ruser_int = current_m_axi_ruser;
+    s_axi_rvalid_int = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+
+            axi_addr_valid_next = 1'b1;
+            axi_id_next = current_s_axi_arid;
+            axi_addr_next = current_s_axi_araddr;
+            axi_len_next = current_s_axi_arlen;
+            axi_size_next = current_s_axi_arsize;
+            axi_burst_next = current_s_axi_arburst;
+            axi_lock_next = current_s_axi_arlock;
+            axi_cache_next = current_s_axi_arcache;
+            axi_prot_next = current_s_axi_prot;
+            axi_qos_next = current_s_axi_arqos;
+            axi_aruser_next = current_s_axi_aruser;
+
+            if (grant_valid) begin
+                s_axi_arready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            if (match) begin
+                m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
+                state_next = STATE_READ;
+            end else begin
+                // no match; return decode error
+                state_next = STATE_READ_DROP;
+            end
+        end
+        STATE_READ: begin
+            // read state; store and forward read response
+            m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
+
+            if (axi_addr_valid_reg) begin
+                m_axi_arvalid_next[m_select_reg] = 1'b1;
+            end
+            axi_addr_valid_next = 1'b0;
+
+            s_axi_rid_int = axi_id_reg;
+            s_axi_rdata_int = current_m_axi_rdata;
+            s_axi_rresp_int = current_m_axi_rresp;
+            s_axi_rlast_int = current_m_axi_rlast;
+            s_axi_ruser_int = current_m_axi_ruser;
+
+            if (m_axi_rready_reg != 0 && current_m_axi_rvalid) begin
+                s_axi_rvalid_int[s_select] = 1'b1;
+
+                if (current_m_axi_rlast) begin
+                    m_axi_rready_next[m_select_reg] = 1'b0;
+                    state_next = STATE_WAIT_IDLE;
+                end else begin
+                    state_next = STATE_READ;
+                end
+            end else begin
+                state_next = STATE_READ;
+            end
+        end
+        STATE_READ_DROP: begin
+            // read drop state; generate decode error read response
+
+            s_axi_rid_int = axi_id_reg;
+            s_axi_rdata_int = '0;
+            s_axi_rresp_int = 2'b11;
+            s_axi_rlast_int = axi_len_reg == 0;
+            s_axi_ruser_int = '0;
+            s_axi_rvalid_int[s_select] = 1'b1;
+
+            if (s_axi_rready_int_reg) begin
+                axi_len_next = axi_len_reg - 1;
+                if (axi_len_reg == 0) begin
+                    state_next = STATE_WAIT_IDLE;
+                end else begin
+                    state_next = STATE_READ_DROP;
+                end
+            end else begin
+                state_next = STATE_READ_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait untl grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    s_axi_arready_reg <= s_axi_arready_next;
+
+    m_axi_arvalid_reg <= m_axi_arvalid_next;
+    m_axi_rready_reg <= m_axi_rready_next;
+
+    m_select_reg <= m_select_next;
+    axi_id_reg <= axi_id_next;
+    axi_addr_reg <= axi_addr_next;
+    axi_addr_valid_reg <= axi_addr_valid_next;
+    axi_len_reg <= axi_len_next;
+    axi_size_reg <= axi_size_next;
+    axi_burst_reg <= axi_burst_next;
+    axi_lock_reg <= axi_lock_next;
+    axi_cache_reg <= axi_cache_next;
+    axi_prot_reg <= axi_prot_next;
+    axi_qos_reg <= axi_qos_next;
+    axi_region_reg <= axi_region_next;
+    axi_aruser_reg <= axi_aruser_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_arready_reg <= '0;
+
+        m_axi_arvalid_reg <= '0;
+        m_axi_rready_reg <= '0;
+    end
+end
+
+// output datapath logic (R channel)
+logic [S_ID_W-1:0]  s_axi_rid_reg    = '0;
+logic [DATA_W-1:0]  s_axi_rdata_reg  = '0;
+logic [1:0]         s_axi_rresp_reg  = 2'd0;
+logic               s_axi_rlast_reg  = 1'b0;
+logic [RUSER_W-1:0] s_axi_ruser_reg  = 1'b0;
+logic [S_COUNT-1:0] s_axi_rvalid_reg = '0, s_axi_rvalid_next;
+
+logic [S_ID_W-1:0]  temp_s_axi_rid_reg    = '0;
+logic [DATA_W-1:0]  temp_s_axi_rdata_reg  = '0;
+logic [1:0]         temp_s_axi_rresp_reg  = 2'd0;
+logic               temp_s_axi_rlast_reg  = 1'b0;
+logic [RUSER_W-1:0] temp_s_axi_ruser_reg  = 1'b0;
+logic [S_COUNT-1:0] temp_s_axi_rvalid_reg = '0, temp_s_axi_rvalid_next;
+
+// datapath control
+logic store_axi_r_int_to_output;
+logic store_axi_r_int_to_temp;
+logic store_axi_r_temp_to_output;
+
+wire [S_COUNT-1:0] s_axi_rready;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_rd[n].rid = s_axi_rid_reg;
+    assign s_axi_rd[n].rdata = s_axi_rdata_reg;
+    assign s_axi_rd[n].rresp = s_axi_rresp_reg;
+    assign s_axi_rd[n].rlast = s_axi_rlast_reg;
+    assign s_axi_rd[n].ruser = RUSER_EN ? s_axi_ruser_reg : '0;
+    assign s_axi_rd[n].rvalid = s_axi_rvalid_reg[n];
+    assign s_axi_rready[n] = s_axi_rd[n].rready;
+end
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign s_axi_rready_int_early = (s_axi_rready & s_axi_rvalid_reg) != 0 || (temp_s_axi_rvalid_reg == 0 && (s_axi_rvalid_reg == 0 || s_axi_rvalid_int == 0));
+
+always_comb begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+    temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+
+    store_axi_r_int_to_output = 1'b0;
+    store_axi_r_int_to_temp = 1'b0;
+    store_axi_r_temp_to_output = 1'b0;
+
+    if (s_axi_rready_int_reg) begin
+        // input is ready
+        if ((s_axi_rready & s_axi_rvalid_reg) != 0 || s_axi_rvalid_reg == 0) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_temp = 1'b1;
+        end
+    end else if ((s_axi_rready & s_axi_rvalid_reg) != 0) begin
+        // input is not ready, but output is ready
+        s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+        temp_s_axi_rvalid_next = '0;
+        store_axi_r_temp_to_output = 1'b1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    s_axi_rvalid_reg <= s_axi_rvalid_next;
+    s_axi_rready_int_reg <= s_axi_rready_int_early;
+    temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
+
+    // datapath
+    if (store_axi_r_int_to_output) begin
+        s_axi_rid_reg <= s_axi_rid_int;
+        s_axi_rdata_reg <= s_axi_rdata_int;
+        s_axi_rresp_reg <= s_axi_rresp_int;
+        s_axi_rlast_reg <= s_axi_rlast_int;
+        s_axi_ruser_reg <= s_axi_ruser_int;
+    end else if (store_axi_r_temp_to_output) begin
+        s_axi_rid_reg <= temp_s_axi_rid_reg;
+        s_axi_rdata_reg <= temp_s_axi_rdata_reg;
+        s_axi_rresp_reg <= temp_s_axi_rresp_reg;
+        s_axi_rlast_reg <= temp_s_axi_rlast_reg;
+        s_axi_ruser_reg <= temp_s_axi_ruser_reg;
+    end
+
+    if (store_axi_r_int_to_temp) begin
+        temp_s_axi_rid_reg <= s_axi_rid_int;
+        temp_s_axi_rdata_reg <= s_axi_rdata_int;
+        temp_s_axi_rresp_reg <= s_axi_rresp_int;
+        temp_s_axi_rlast_reg <= s_axi_rlast_int;
+        temp_s_axi_ruser_reg <= s_axi_ruser_int;
+    end
+
+    if (rst) begin
+        s_axi_rvalid_reg <= '0;
+        s_axi_rready_int_reg <= 1'b0;
+        temp_s_axi_rvalid_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_interconnect_wr.sv

@@ -0,0 +1,668 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_wr[0].DATA_W;
+localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
+localparam STRB_W = s_axi_wr[0].STRB_W;
+localparam S_ID_W = s_axi_wr[0].ID_W;
+localparam M_ID_W = m_axi_wr[0].ID_W;
+localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
+localparam WUSER_W = s_axi_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
+localparam BUSER_W = s_axi_wr[0].BUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axi_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    if (M_REGIONS < 1 || M_REGIONS > 16) begin
+        $error("Error: M_REGIONS must be between 1 and 16 (instance %m)");
+        $finish;
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axi_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_WRITE = 3'd2,
+    STATE_WRITE_RESP = 3'd3,
+    STATE_WRITE_DROP = 3'd4,
+    STATE_WAIT_IDLE = 3'd5;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next;
+logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next;
+logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
+logic [7:0] axi_len_reg = 8'd0, axi_len_next;
+logic [2:0] axi_size_reg = 3'd0, axi_size_next;
+logic [1:0] axi_burst_reg = 2'd0, axi_burst_next;
+logic axi_lock_reg = 1'b0, axi_lock_next;
+logic [3:0] axi_cache_reg = 4'd0, axi_cache_next;
+logic [2:0] axi_prot_reg = 3'b000, axi_prot_next;
+logic [3:0] axi_qos_reg = 4'd0, axi_qos_next;
+logic [3:0] axi_region_reg = 4'd0, axi_region_next;
+logic [AWUSER_W-1:0] axi_awuser_reg = '0, axi_awuser_next;
+logic [1:0] axi_bresp_reg = 2'b00, axi_bresp_next;
+logic [BUSER_W-1:0] axi_buser_reg = '0, axi_buser_next;
+
+logic [S_COUNT-1:0] s_axi_awready_reg = '0, s_axi_awready_next;
+logic [S_COUNT-1:0] s_axi_wready_reg = '0, s_axi_wready_next;
+logic [S_COUNT-1:0] s_axi_bvalid_reg = '0, s_axi_bvalid_next;
+
+logic [M_COUNT-1:0] m_axi_awvalid_reg = '0, m_axi_awvalid_next;
+logic [M_COUNT-1:0] m_axi_bready_reg = '0, m_axi_bready_next;
+
+// internal datapath
+logic  [DATA_W-1:0]   m_axi_wdata_int;
+logic  [STRB_W-1:0]   m_axi_wstrb_int;
+logic                 m_axi_wlast_int;
+logic  [WUSER_W-1:0]  m_axi_wuser_int;
+logic  [M_COUNT-1:0]  m_axi_wvalid_int;
+logic                 m_axi_wready_int_reg = 1'b0;
+wire                  m_axi_wready_int_early;
+
+// unpack interface array
+wire [S_ID_W-1:0]    s_axi_awid[S_COUNT];
+wire [ADDR_W-1:0]    s_axi_addr[S_COUNT];
+wire [7:0]           s_axi_awlen[S_COUNT];
+wire [2:0]           s_axi_awsize[S_COUNT];
+wire [1:0]           s_axi_awburst[S_COUNT];
+wire                 s_axi_awlock[S_COUNT];
+wire [3:0]           s_axi_awcache[S_COUNT];
+wire [2:0]           s_axi_awprot[S_COUNT];
+wire [3:0]           s_axi_awqos[S_COUNT];
+wire [AWUSER_W-1:0]  s_axi_awuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_awvalid;
+wire [DATA_W-1:0]    s_axi_wdata[S_COUNT];
+wire [STRB_W-1:0]    s_axi_wstrb[S_COUNT];
+wire                 s_axi_wlast[S_COUNT];
+wire [WUSER_W-1:0]   s_axi_wuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_wvalid;
+wire [S_COUNT-1:0]   s_axi_bready;
+
+wire [M_COUNT-1:0]   m_axi_awready;
+wire [M_ID_W-1:0]    m_axi_bid[M_COUNT];
+wire [1:0]           m_axi_bresp[M_COUNT];
+wire [BUSER_W-1:0]   m_axi_buser[M_COUNT];
+wire [M_COUNT-1:0]   m_axi_bvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_awid[n] = s_axi_wr[n].awid;
+    assign s_axi_addr[n] = s_axi_wr[n].awaddr;
+    assign s_axi_awlen[n] = s_axi_wr[n].awlen;
+    assign s_axi_awsize[n] = s_axi_wr[n].awsize;
+    assign s_axi_awburst[n] = s_axi_wr[n].awburst;
+    assign s_axi_awlock[n] = s_axi_wr[n].awlock;
+    assign s_axi_awcache[n] = s_axi_wr[n].awcache;
+    assign s_axi_awprot[n] = s_axi_wr[n].awprot;
+    assign s_axi_awqos[n] = s_axi_wr[n].awqos;
+    assign s_axi_awuser[n] = s_axi_wr[n].awuser;
+    assign s_axi_awvalid[n] = s_axi_wr[n].awvalid;
+    assign s_axi_wr[n].awready = s_axi_awready_reg[n];
+    assign s_axi_wdata[n] = s_axi_wr[n].wdata;
+    assign s_axi_wstrb[n] = s_axi_wr[n].wstrb;
+    assign s_axi_wlast[n] = s_axi_wr[n].wlast;
+    assign s_axi_wuser[n] = s_axi_wr[n].wuser;
+    assign s_axi_wvalid[n] = s_axi_wr[n].wvalid;
+    assign s_axi_wr[n].wready = s_axi_wready_reg[n];
+    assign s_axi_wr[n].bid = axi_id_reg;
+    assign s_axi_wr[n].bresp = axi_bresp_reg;
+    assign s_axi_wr[n].buser = BUSER_EN ? axi_buser_reg : '0;
+    assign s_axi_wr[n].bvalid = s_axi_bvalid_reg[n];
+    assign s_axi_bready[n] = s_axi_wr[n].bready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_wr[n].awid = axi_id_reg;
+    assign m_axi_wr[n].awaddr = AXI_M_ADDR_W'(axi_addr_reg);
+    assign m_axi_wr[n].awlen = axi_len_reg;
+    assign m_axi_wr[n].awsize = axi_size_reg;
+    assign m_axi_wr[n].awburst = axi_burst_reg;
+    assign m_axi_wr[n].awlock = axi_lock_reg;
+    assign m_axi_wr[n].awcache = axi_cache_reg;
+    assign m_axi_wr[n].awprot = axi_prot_reg;
+    assign m_axi_wr[n].awqos = axi_qos_reg;
+    assign m_axi_wr[n].awuser = AWUSER_EN ? axi_awuser_reg : '0;
+    assign m_axi_wr[n].awvalid = m_axi_awvalid_reg[n];
+    assign m_axi_awready[n] = m_axi_wr[n].awready;
+    assign m_axi_bid[n] = m_axi_wr[n].bid;
+    assign m_axi_bresp[n] = m_axi_wr[n].bresp;
+    assign m_axi_buser[n] = m_axi_wr[n].buser;
+    assign m_axi_bvalid[n] = m_axi_wr[n].bvalid;
+    assign m_axi_wr[n].bready = m_axi_bready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [S_ID_W-1:0]    current_s_axi_awid    = s_axi_awid[s_select];
+wire [ADDR_W-1:0]    current_s_axi_addr    = s_axi_addr[s_select];
+wire [7:0]           current_s_axi_awlen   = s_axi_awlen[s_select];
+wire [2:0]           current_s_axi_awsize  = s_axi_awsize[s_select];
+wire [1:0]           current_s_axi_awburst = s_axi_awburst[s_select];
+wire                 current_s_axi_awlock  = s_axi_awlock[s_select];
+wire [3:0]           current_s_axi_awcache = s_axi_awcache[s_select];
+wire [2:0]           current_s_axi_awprot  = s_axi_awprot[s_select];
+wire [3:0]           current_s_axi_awqos   = s_axi_awqos[s_select];
+wire [AWUSER_W-1:0]  current_s_axi_awuser  = s_axi_awuser[s_select];
+wire                 current_s_axi_awvalid = s_axi_awvalid[s_select];
+wire [DATA_W-1:0]    current_s_axi_wdata   = s_axi_wdata[s_select];
+wire [STRB_W-1:0]    current_s_axi_wstrb   = s_axi_wstrb[s_select];
+wire                 current_s_axi_wlast   = s_axi_wlast[s_select];
+wire [WUSER_W-1:0]   current_s_axi_wuser   = s_axi_wuser[s_select];
+wire                 current_s_axi_wvalid  = s_axi_wvalid[s_select];
+wire                 current_s_axi_bready  = s_axi_bready[s_select];
+
+// master side mux
+wire                 current_m_axi_awready = m_axi_awready[m_select_reg];
+wire                 current_m_axi_wready  = m_axi_wready[m_select_reg];
+wire [M_ID_W-1:0]    current_m_axi_bid     = m_axi_bid[m_select_reg];
+wire [1:0]           current_m_axi_bresp   = m_axi_bresp[m_select_reg];
+wire [BUSER_W-1:0]   current_m_axi_buser   = m_axi_buser[m_select_reg];
+wire                 current_m_axi_bvalid  = m_axi_bvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+assign req = s_axi_awvalid;
+assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axi_id_next = axi_id_reg;
+    axi_addr_next = axi_addr_reg;
+    axi_addr_valid_next = axi_addr_valid_reg;
+    axi_len_next = axi_len_reg;
+    axi_size_next = axi_size_reg;
+    axi_burst_next = axi_burst_reg;
+    axi_lock_next = axi_lock_reg;
+    axi_cache_next = axi_cache_reg;
+    axi_prot_next = axi_prot_reg;
+    axi_qos_next = axi_qos_reg;
+    axi_region_next = axi_region_reg;
+    axi_awuser_next = axi_awuser_reg;
+    axi_bresp_next = axi_bresp_reg;
+    axi_buser_next = axi_buser_reg;
+
+    s_axi_awready_next = '0;
+    s_axi_wready_next = '0;
+    s_axi_bvalid_next = s_axi_bvalid_reg & ~s_axi_bready;
+
+    m_axi_awvalid_next = m_axi_awvalid_reg & ~m_axi_awready;
+    m_axi_bready_next = '0;
+
+    m_axi_wdata_int = current_s_axi_wdata;
+    m_axi_wstrb_int = current_s_axi_wstrb;
+    m_axi_wlast_int = current_s_axi_wlast;
+    m_axi_wuser_int = current_s_axi_wuser;
+    m_axi_wvalid_int = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+
+            axi_addr_valid_next = 1'b1;
+            axi_id_next = current_s_axi_awid;
+            axi_addr_next = current_s_axi_addr;
+            axi_len_next = current_s_axi_awlen;
+            axi_size_next = current_s_axi_awsize;
+            axi_burst_next = current_s_axi_awburst;
+            axi_lock_next = current_s_axi_awlock;
+            axi_cache_next = current_s_axi_awcache;
+            axi_prot_next = current_s_axi_awprot;
+            axi_qos_next = current_s_axi_awqos;
+            axi_awuser_next = current_s_axi_awuser;
+
+            if (grant_valid) begin
+                s_axi_awready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            axi_bresp_next = 2'b11;
+
+            if (match) begin
+                s_axi_wready_next[s_select] = m_axi_wready_int_early;
+                state_next = STATE_WRITE;
+            end else begin
+                // no match; return decode error
+                s_axi_wready_next[s_select] = 1'b1;
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WRITE: begin
+            // write state; store and forward write data
+            s_axi_wready_next[s_select] = m_axi_wready_int_early;
+
+            if (axi_addr_valid_reg) begin
+                m_axi_awvalid_next[m_select_reg] = 1'b1;
+            end
+            axi_addr_valid_next = 1'b0;
+
+            m_axi_wdata_int = current_s_axi_wdata;
+            m_axi_wstrb_int = current_s_axi_wstrb;
+            m_axi_wlast_int = current_s_axi_wlast;
+            m_axi_wuser_int = current_s_axi_wuser;
+
+            if (s_axi_wready_reg != 0 && current_s_axi_wvalid) begin
+                m_axi_wvalid_int[m_select_reg] = 1'b1;
+
+                if (current_s_axi_wlast) begin
+                    s_axi_wready_next[s_select] = 1'b0;
+                    m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
+                    state_next = STATE_WRITE_RESP;
+                end else begin
+                    state_next = STATE_WRITE;
+                end
+            end else begin
+                state_next = STATE_WRITE;
+            end
+        end
+        STATE_WRITE_RESP: begin
+            // write response state; store and forward write response
+            m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
+
+            if (m_axi_bready_reg != 0 && current_m_axi_bvalid) begin
+                m_axi_bready_next[m_select_reg] = 1'b0;
+                axi_bresp_next = current_m_axi_bresp;
+                s_axi_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_RESP;
+            end
+        end
+        STATE_WRITE_DROP: begin
+            // write drop state; drop write data
+            s_axi_wready_next[s_select] = 1'b1;
+
+            axi_addr_valid_next = 1'b0;
+
+            if (s_axi_wready_reg != 0 && current_s_axi_wvalid && current_s_axi_wlast) begin
+                s_axi_wready_next[s_select] = 1'b0;
+                s_axi_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait untl grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    s_axi_awready_reg <= s_axi_awready_next;
+    s_axi_wready_reg <= s_axi_wready_next;
+    s_axi_bvalid_reg <= s_axi_bvalid_next;
+
+    m_axi_awvalid_reg <= m_axi_awvalid_next;
+    m_axi_bready_reg <= m_axi_bready_next;
+
+    m_select_reg <= m_select_next;
+    axi_id_reg <= axi_id_next;
+    axi_addr_reg <= axi_addr_next;
+    axi_addr_valid_reg <= axi_addr_valid_next;
+    axi_len_reg <= axi_len_next;
+    axi_size_reg <= axi_size_next;
+    axi_burst_reg <= axi_burst_next;
+    axi_lock_reg <= axi_lock_next;
+    axi_cache_reg <= axi_cache_next;
+    axi_prot_reg <= axi_prot_next;
+    axi_qos_reg <= axi_qos_next;
+    axi_region_reg <= axi_region_next;
+    axi_awuser_reg <= axi_awuser_next;
+    axi_bresp_reg <= axi_bresp_next;
+    axi_buser_reg <= axi_buser_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_awready_reg <= '0;
+        s_axi_wready_reg <= '0;
+        s_axi_bvalid_reg <= '0;
+
+        m_axi_awvalid_reg <= '0;
+        m_axi_bready_reg <= '0;
+    end
+end
+
+// output datapath logic (W channel)
+logic [DATA_W-1:0]  m_axi_wdata_reg  = '0;
+logic [STRB_W-1:0]  m_axi_wstrb_reg  = '0;
+logic               m_axi_wlast_reg  = 1'b0;
+logic [WUSER_W-1:0] m_axi_wuser_reg  = 1'b0;
+logic [M_COUNT-1:0] m_axi_wvalid_reg = '0, m_axi_wvalid_next;
+
+logic [DATA_W-1:0]  temp_m_axi_wdata_reg  = '0;
+logic [STRB_W-1:0]  temp_m_axi_wstrb_reg  = '0;
+logic               temp_m_axi_wlast_reg  = 1'b0;
+logic [WUSER_W-1:0] temp_m_axi_wuser_reg  = 1'b0;
+logic [M_COUNT-1:0] temp_m_axi_wvalid_reg = '0, temp_m_axi_wvalid_next;
+
+// datapath control
+logic store_axi_w_int_to_output;
+logic store_axi_w_int_to_temp;
+logic store_axi_w_temp_to_output;
+
+wire [M_COUNT-1:0] m_axi_wready;
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_wr[n].wdata = m_axi_wdata_reg;
+    assign m_axi_wr[n].wstrb = m_axi_wstrb_reg;
+    assign m_axi_wr[n].wlast = m_axi_wlast_reg;
+    assign m_axi_wr[n].wuser = WUSER_EN ? m_axi_wuser_reg : '0;
+    assign m_axi_wr[n].wvalid = m_axi_wvalid_reg[n];
+    assign m_axi_wready[n] = m_axi_wr[n].wready;
+end
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axi_wready_int_early = (m_axi_wready & m_axi_wvalid_reg) != 0 || (temp_m_axi_wvalid_reg == 0 && (m_axi_wvalid_reg == 0 || m_axi_wvalid_int == 0));
+
+always_comb begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_int_to_output = 1'b0;
+    store_axi_w_int_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (m_axi_wready_int_reg) begin
+        // input is ready
+        if ((m_axi_wready & m_axi_wvalid_reg) != 0 || m_axi_wvalid_reg == 0) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_temp = 1'b1;
+        end
+    end else if ((m_axi_wready & m_axi_wvalid_reg) != 0) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = '0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    m_axi_wvalid_reg <= m_axi_wvalid_next;
+    m_axi_wready_int_reg <= m_axi_wready_int_early;
+    temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+
+    // datapath
+    if (store_axi_w_int_to_output) begin
+        m_axi_wdata_reg <= m_axi_wdata_int;
+        m_axi_wstrb_reg <= m_axi_wstrb_int;
+        m_axi_wlast_reg <= m_axi_wlast_int;
+        m_axi_wuser_reg <= m_axi_wuser_int;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end
+
+    if (store_axi_w_int_to_temp) begin
+        temp_m_axi_wdata_reg <= m_axi_wdata_int;
+        temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
+        temp_m_axi_wlast_reg <= m_axi_wlast_int;
+        temp_m_axi_wuser_reg <= m_axi_wuser_int;
+    end
+
+    if (rst) begin
+        m_axi_wvalid_reg <= '0;
+        m_axi_wready_int_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_apb_adapter.sv

@@ -73,7 +73,7 @@ if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
     $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
 
 if (APB_BYTE_W * APB_STRB_W != APB_DATA_W)
-    $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)");
+    $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)");
 
 if (AXIL_BYTE_W != APB_BYTE_W)
     $fatal(0, "Error: byte size mismatch (instance %m)");
@@ -248,7 +248,7 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
         endcase
     end
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         state_reg <= state_next;
 
         last_read_reg <= last_read_next;
@@ -287,7 +287,7 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
             s_axil_rvalid_reg <= 1'b0;
 
             m_apb_psel_reg <= 1'b0;
-            m_apb_penable_reg <= 1'b0;            
+            m_apb_penable_reg <= 1'b0;
         end
     end
 
@@ -447,7 +447,7 @@ end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
         endcase
     end
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         state_reg <= state_next;
 
         last_read_reg <= last_read_next;
@@ -486,7 +486,7 @@ end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
             s_axil_rvalid_reg <= 1'b0;
 
             m_apb_psel_reg <= 1'b0;
-            m_apb_penable_reg <= 1'b0;            
+            m_apb_penable_reg <= 1'b0;
         end
     end
 
@@ -726,7 +726,7 @@ end else begin : downsize
             s_axil_rvalid_reg <= 1'b0;
 
             m_apb_psel_reg <= 1'b0;
-            m_apb_penable_reg <= 1'b0;   
+            m_apb_penable_reg <= 1'b0;
         end
     end
 

src/axi/rtl/taxi_axil_crossbar.f

@@ -0,0 +1,3 @@
+taxi_axil_crossbar.sv
+taxi_axil_crossbar_wr.f
+taxi_axil_crossbar_rd.f

src/axi/rtl/taxi_axil_crossbar.sv

@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar
+ */
+module taxi_axil_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT],
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+taxi_axil_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI lite slave interfaces
+     */
+    .s_axil_wr(s_axil_wr),
+
+    /*
+     * AXI lite master interfaces
+     */
+    .m_axil_wr(m_axil_wr)
+);
+
+taxi_axil_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI lite slave interfaces
+     */
+    .s_axil_rd(s_axil_rd),
+
+    /*
+     * AXI lite master interfaces
+     */
+    .m_axil_rd(m_axil_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_addr.sv

@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar address decode and admission control
+ */
+module taxi_axil_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Select signal width
+    parameter SEL_W = $clog2(M_COUNT),
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Address width in bits for address decoding
+    parameter STRB_W = 4,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * Address input
+     */
+    input  wire logic [ADDR_W-1:0]  s_axil_aaddr,
+    input  wire logic [2:0]         s_axil_aprot,
+    input  wire logic               s_axil_avalid,
+    output wire logic               s_axil_aready,
+
+    /*
+     * Select output
+     */
+    output wire logic [SEL_W-1:0]   m_select,
+    output wire logic               m_axil_avalid,
+    input  wire logic               m_axil_aready,
+
+    /*
+     * Write command output
+     */
+    output wire logic [SEL_W-1:0]   m_wc_select,
+    output wire logic               m_wc_decerr,
+    output wire logic               m_wc_valid,
+    input  wire logic               m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire logic [SEL_W-1:0]   m_rc_select,
+    output wire logic               m_rc_decerr,
+    output wire logic               m_rc_valid,
+    input  wire logic               m_rc_ready
+);
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (M_REGIONS < 1)
+    $fatal(0, "Error: M_REGIONS must be at least 1 (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_crossbar_addr instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [0:0]
+    STATE_IDLE = 1'd0,
+    STATE_DECODE = 1'd1;
+
+logic [0:0] state_reg = STATE_IDLE, state_next;
+
+logic s_axil_aready_reg = 1'b0, s_axil_aready_next;
+
+logic [SEL_W-1:0] m_select_reg = '0, m_select_next;
+logic m_axil_avalid_reg = 1'b0, m_axil_avalid_next;
+logic m_decerr_reg = 1'b0, m_decerr_next;
+logic m_wc_valid_reg = 1'b0, m_wc_valid_next;
+logic m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axil_aready = s_axil_aready_reg;
+
+assign m_select = m_select_reg;
+assign m_axil_avalid = m_axil_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_select = m_select_reg;
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+logic match;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    s_axil_aready_next = 1'b0;
+
+    m_select_next = m_select_reg;
+    m_axil_avalid_next = m_axil_avalid_reg && !m_axil_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axil_aready_next = 1'b0;
+
+            if (s_axil_avalid && !s_axil_aready) begin
+                match = 1'b0;
+                for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                    for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_axil_aprot[1]) && M_CONNECT_INT[i][S] && (s_axil_aaddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                            m_select_next = SEL_W'(i);
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    m_axil_avalid_next = 1'b1;
+                    m_decerr_next = 1'b0;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end else begin
+                    // decode error
+                    m_axil_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axil_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axil_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+    s_axil_aready_reg <= s_axil_aready_next;
+    m_axil_avalid_reg <= m_axil_avalid_next;
+    m_wc_valid_reg <= m_wc_valid_next;
+    m_rc_valid_reg <= m_rc_valid_next;
+
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axil_aready_reg <= 1'b0;
+        m_axil_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_rd.f

@@ -0,0 +1,6 @@
+taxi_axil_crossbar_rd.sv
+taxi_axil_crossbar_addr.sv
+taxi_axil_register_rd.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_crossbar_rd.sv

@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar (read)
+ */
+module taxi_axil_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_rd[0].DATA_W;
+localparam S_ADDR_W = s_axil_rd[0].ADDR_W;
+localparam STRB_W = s_axil_rd[0].STRB_W;
+localparam logic ARUSER_EN = s_axil_rd[0].ARUSER_EN && m_axil_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
+localparam RUSER_W = s_axil_rd[0].RUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axil_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+wire [ADDR_W-1:0]    int_s_axil_araddr[S_COUNT];
+wire [2:0]           int_s_axil_arprot[S_COUNT];
+wire [ARUSER_W-1:0]  int_s_axil_aruser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_arvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_arready[M_COUNT];
+
+wire [DATA_W-1:0]    int_m_axil_rdata[M_COUNT];
+wire [1:0]           int_m_axil_rresp[M_COUNT];
+wire [RUSER_W-1:0]   int_m_axil_ruser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axil_rvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axil_rready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(s_axil_rd[0].DATA_W),
+        .ADDR_W(s_axil_rd[0].ADDR_W),
+        .STRB_W(s_axil_rd[0].STRB_W),
+        .ARUSER_EN(s_axil_rd[0].ARUSER_EN),
+        .ARUSER_W(s_axil_rd[0].ARUSER_W),
+        .RUSER_EN(s_axil_rd[0].RUSER_EN),
+        .RUSER_W(s_axil_rd[0].RUSER_W)
+    ) int_axil();
+
+    // S side register
+    taxi_axil_register_rd #(
+        .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+        .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_rd(s_axil_rd[m]),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_rd(int_axil)
+    );
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = 0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = 0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic fifo_decerr[2**FIFO_AW];
+
+    wire [CL_M_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_decerr;
+    wire fifo_wr_en;
+
+    logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = 0;
+    logic fifo_rd_decerr_reg = 0;
+    logic fifo_rd_valid_reg = 0;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    integer i;
+
+    initial begin
+        for (i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = 0;
+            fifo_decerr[i] = 0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+
+        fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+        if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+            fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_valid_reg <= 1'b1;
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= 0;
+            fifo_rd_ptr_reg <= 0;
+            fifo_rd_valid_reg <= 1'b0;
+        end
+    end
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axil_avalid;
+    wire m_axil_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_rc_select;
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    taxi_axil_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .STRB_W(STRB_W),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(0)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axil_aaddr(int_axil.araddr),
+        .s_axil_aprot(int_axil.arprot),
+        .s_axil_avalid(int_axil.arvalid),
+        .s_axil_aready(int_axil.arready),
+
+        /*
+         * Address output
+         */
+        .m_select(a_select),
+        .m_axil_avalid(m_axil_avalid),
+        .m_axil_aready(m_axil_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(),
+        .m_wc_decerr(),
+        .m_wc_valid(),
+        .m_wc_ready(1'b1),
+
+        /*
+         * Response command output
+         */
+        .m_rc_select(m_rc_select),
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready)
+    );
+
+    assign int_s_axil_araddr[m] = int_axil.araddr;
+    assign int_s_axil_arprot[m] = int_axil.arprot;
+    assign int_s_axil_aruser[m] = int_axil.aruser;
+
+    always_comb begin
+        int_axil_arvalid[m] = '0;
+        int_axil_arvalid[m][a_select] = m_axil_avalid;
+    end
+    assign m_axil_aready = int_axil_arready[a_select][m];
+
+    // response handling
+    assign fifo_wr_select = m_rc_select;
+    assign fifo_wr_decerr = m_rc_decerr;
+    assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg;
+    assign m_rc_ready = !fifo_half_full_reg;
+
+    // write response handling
+    wire [CL_M_COUNT_INT-1:0] r_select = M_COUNT > 1 ? fifo_rd_select_reg : '0;
+    wire r_decerr = fifo_rd_decerr_reg;
+    wire r_valid = fifo_rd_valid_reg;
+
+    // read response mux
+    assign int_axil.rdata  = r_decerr ? '0 : int_m_axil_rdata[r_select];
+    assign int_axil.rresp  = r_decerr ? 2'b11 : int_m_axil_rresp[r_select];
+    assign int_axil.ruser  = r_decerr ? '0 : int_m_axil_ruser[r_select];
+    assign int_axil.rvalid = (r_decerr ? 1'b1 : int_axil_rvalid[r_select][m]) && r_valid;
+
+    always_comb begin
+        int_axil_rready[m] = '0;
+        int_axil_rready[m][r_select] = r_valid && int_axil.rready;
+    end
+
+    assign fifo_rd_en = int_axil.rvalid && int_axil.rready && r_valid;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(m_axil_rd[0].DATA_W),
+        .ADDR_W(m_axil_rd[0].ADDR_W),
+        .STRB_W(m_axil_rd[0].STRB_W),
+        .ARUSER_EN(m_axil_rd[0].ARUSER_EN),
+        .ARUSER_W(m_axil_rd[0].ARUSER_W),
+        .RUSER_EN(m_axil_rd[0].RUSER_EN),
+        .RUSER_W(m_axil_rd[0].RUSER_W)
+    ) int_axil();
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    wire [CL_S_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_en;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+        if (fifo_rd_en) begin
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+        end
+    end
+
+    // address arbitration
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    assign int_axil.araddr   = AXIL_M_ADDR_W'(int_s_axil_araddr[a_grant_index]);
+    assign int_axil.arprot   = int_s_axil_arprot[a_grant_index];
+    assign int_axil.aruser   = int_s_axil_aruser[a_grant_index];
+    assign int_axil.arvalid  = int_axil_arvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axil_arready[n] = '0;
+        int_axil_arready[n][a_grant_index] = a_grant_valid && int_axil.arready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axil_arvalid[m][n] && !a_grant_valid && !fifo_half_full_reg;
+        assign a_ack[m] = a_grant[m] && int_axil_arvalid[m][n] && int_axil.arready;
+    end
+
+    assign fifo_wr_select = a_grant_index;
+    assign fifo_wr_en = int_axil.arvalid && int_axil.arready && a_grant_valid;
+
+    // read response forwarding
+    wire [CL_S_COUNT_INT-1:0] r_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0;
+
+    assign int_m_axil_rdata[n] = int_axil.rdata;
+    assign int_m_axil_rresp[n] = int_axil.rresp;
+    assign int_m_axil_ruser[n] = int_axil.ruser;
+
+    always_comb begin
+        int_axil_rvalid[n] = '0;
+        int_axil_rvalid[n][r_select] = int_axil.rvalid;
+    end
+    assign int_axil.rready = int_axil_rready[r_select][n];
+
+    assign fifo_rd_en = int_axil.rvalid && int_axil.rready;
+
+    // M side register
+    taxi_axil_register_rd #(
+        .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+        .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_rd(int_axil),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_rd(m_axil_rd[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_wr.f

@@ -0,0 +1,6 @@
+taxi_axil_crossbar_wr.sv
+taxi_axil_crossbar_addr.sv
+taxi_axil_register_wr.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_crossbar_wr.sv

@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar (write)
+ */
+module taxi_axil_crossbar_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_wr[0].DATA_W;
+localparam S_ADDR_W = s_axil_wr[0].ADDR_W;
+localparam STRB_W = s_axil_wr[0].STRB_W;
+localparam logic AWUSER_EN = s_axil_wr[0].AWUSER_EN && m_axil_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axil_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axil_wr[0].WUSER_EN && m_axil_wr[0].WUSER_EN;
+localparam WUSER_W = s_axil_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
+localparam BUSER_W = s_axil_wr[0].BUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axil_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+wire [ADDR_W-1:0]    int_s_axil_awaddr[S_COUNT];
+wire [2:0]           int_s_axil_awprot[S_COUNT];
+wire [AWUSER_W-1:0]  int_s_axil_awuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_awvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_awready[M_COUNT];
+
+wire [DATA_W-1:0]    int_s_axil_wdata[S_COUNT];
+wire [STRB_W-1:0]    int_s_axil_wstrb[S_COUNT];
+wire [WUSER_W-1:0]   int_s_axil_wuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_wvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_wready[M_COUNT];
+
+wire [1:0]           int_m_axil_bresp[M_COUNT];
+wire [BUSER_W-1:0]   int_m_axil_buser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axil_bvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axil_bready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(s_axil_wr[0].DATA_W),
+        .ADDR_W(s_axil_wr[0].ADDR_W),
+        .STRB_W(s_axil_wr[0].STRB_W),
+        .AWUSER_EN(s_axil_wr[0].AWUSER_EN),
+        .AWUSER_W(s_axil_wr[0].AWUSER_W),
+        .WUSER_EN(s_axil_wr[0].WUSER_EN),
+        .WUSER_W(s_axil_wr[0].WUSER_W),
+        .BUSER_EN(s_axil_wr[0].BUSER_EN),
+        .BUSER_W(s_axil_wr[0].BUSER_W)
+    ) int_axil();
+
+    // S side register
+    taxi_axil_register_wr #(
+        .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+        .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+        .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_wr(s_axil_wr[m]),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_wr(int_axil)
+    );
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic fifo_decerr[2**FIFO_AW];
+
+    wire [CL_M_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_decerr;
+    wire fifo_wr_en;
+
+    logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = '0;
+    logic fifo_rd_decerr_reg = 1'b0;
+    logic fifo_rd_valid_reg = 1'b0;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+            fifo_decerr[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+
+        fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+        if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+            fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_valid_reg <= 1'b1;
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+            fifo_rd_valid_reg <= 1'b0;
+        end
+    end
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axil_avalid;
+    wire m_axil_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_wc_select;
+    wire m_wc_decerr;
+    wire m_wc_valid;
+    wire m_wc_ready;
+
+    wire [CL_M_COUNT_INT-1:0] m_rc_select;
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    taxi_axil_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .STRB_W(STRB_W),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(1)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axil_aaddr(int_axil.awaddr),
+        .s_axil_aprot(int_axil.awprot),
+        .s_axil_avalid(int_axil.awvalid),
+        .s_axil_aready(int_axil.awready),
+
+        /*
+         * Address output
+         */
+        .m_select(a_select),
+        .m_axil_avalid(m_axil_avalid),
+        .m_axil_aready(m_axil_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(m_wc_select),
+        .m_wc_decerr(m_wc_decerr),
+        .m_wc_valid(m_wc_valid),
+        .m_wc_ready(m_wc_ready),
+
+        /*
+         * Response command output
+         */
+        .m_rc_select(m_rc_select),
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready)
+    );
+
+    assign int_s_axil_awaddr[m] = int_axil.awaddr;
+    assign int_s_axil_awprot[m] = int_axil.awprot;
+    assign int_s_axil_awuser[m] = int_axil.awuser;
+
+    always_comb begin
+        int_axil_awvalid[m] = '0;
+        int_axil_awvalid[m][a_select] = m_axil_avalid;
+    end
+    assign m_axil_aready = int_axil_awready[a_select][m];
+
+    // write command handling
+    logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_drop_reg = 1'b0, w_drop_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+
+    assign m_wc_ready = !w_select_valid_reg;
+
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_drop_next = w_drop_reg && !(int_axil.wvalid && int_axil.wready);
+        w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready);
+
+        if (m_wc_valid && !w_select_valid_reg) begin
+            w_select_next = m_wc_select;
+            w_drop_next = m_wc_decerr;
+            w_select_valid_next = m_wc_valid;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_reg <= w_select_next;
+        w_drop_reg <= w_drop_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+        end
+    end
+
+    // write data forwarding
+    assign int_s_axil_wdata[m] = int_axil.wdata;
+    assign int_s_axil_wstrb[m] = int_axil.wstrb;
+    assign int_s_axil_wuser[m] = int_axil.wuser;
+
+    always_comb begin
+        int_axil_wvalid[m] = '0;
+        int_axil_wvalid[m][w_select_reg] = int_axil.wvalid && w_select_valid_reg && !w_drop_reg;
+    end
+    assign int_axil.wready = int_axil_wready[w_select_reg][m] || w_drop_reg;
+
+    // response handling
+    assign fifo_wr_select = m_rc_select;
+    assign fifo_wr_decerr = m_rc_decerr;
+    assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg;
+    assign m_rc_ready = !fifo_half_full_reg;
+
+    // write response handling
+    wire [CL_M_COUNT_INT-1:0] b_select = M_COUNT > 1 ? fifo_rd_select_reg : '0;
+    wire b_decerr = fifo_rd_decerr_reg;
+    wire b_valid = fifo_rd_valid_reg;
+
+    // write response mux
+    assign int_axil.bresp = b_decerr ? 2'b11 : int_m_axil_bresp[b_select];
+    assign int_axil.buser = b_decerr ? '0 : int_m_axil_buser[b_select];
+    assign int_axil.bvalid = (b_decerr ? 1'b1 : int_axil_bvalid[b_select][m]) && b_valid;
+
+    always_comb begin
+        int_axil_bready[m] = '0;
+        int_axil_bready[m][b_select] = b_valid && int_axil.bready;
+    end
+
+    assign fifo_rd_en = int_axil.bvalid && int_axil.bready && b_valid;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(m_axil_wr[0].DATA_W),
+        .ADDR_W(m_axil_wr[0].ADDR_W),
+        .STRB_W(m_axil_wr[0].STRB_W),
+        .AWUSER_EN(m_axil_wr[0].AWUSER_EN),
+        .AWUSER_W(m_axil_wr[0].AWUSER_W),
+        .WUSER_EN(m_axil_wr[0].WUSER_EN),
+        .WUSER_W(m_axil_wr[0].WUSER_W),
+        .BUSER_EN(m_axil_wr[0].BUSER_EN),
+        .BUSER_W(m_axil_wr[0].BUSER_W)
+    ) int_axil();
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    wire [CL_S_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_en;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+        if (fifo_rd_en) begin
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+        end
+    end
+
+    // address arbitration
+    logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+    logic w_select_new_reg = 1'b0, w_select_new_next;
+
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    assign int_axil.awaddr   = AXIL_M_ADDR_W'(int_s_axil_awaddr[a_grant_index]);
+    assign int_axil.awprot   = int_s_axil_awprot[a_grant_index];
+    assign int_axil.awuser   = int_s_axil_awuser[a_grant_index];
+    assign int_axil.awvalid  = int_axil_awvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axil_awready[n] = '0;
+        int_axil_awready[n][a_grant_index] = a_grant_valid && int_axil.awready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axil_awvalid[m][n] && !a_grant_valid && !fifo_half_full_reg && !w_select_valid_next;
+        assign a_ack[m] = a_grant[m] && int_axil_awvalid[m][n] && int_axil.awready;
+    end
+
+    assign fifo_wr_select = a_grant_index;
+    assign fifo_wr_en = int_axil.awvalid && int_axil.awready && a_grant_valid;
+
+    // write data mux
+    assign int_axil.wdata   = int_s_axil_wdata[w_select_reg];
+    assign int_axil.wstrb   = int_s_axil_wstrb[w_select_reg];
+    assign int_axil.wuser   = int_s_axil_wuser[w_select_reg];
+    assign int_axil.wvalid  = int_axil_wvalid[w_select_reg][n] && w_select_valid_reg;
+
+    always_comb begin
+        int_axil_wready[n] = '0;
+        int_axil_wready[n][w_select_reg] = w_select_valid_reg && int_axil.wready;
+    end
+
+    // write data routing
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready);
+        w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0;
+
+        if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+            w_select_next = a_grant_index;
+            w_select_valid_next = a_grant_valid;
+            w_select_new_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_reg <= w_select_next;
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_new_reg <= w_select_new_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+            w_select_new_reg <= 1'b1;
+        end
+    end
+
+    // write response forwarding
+    wire [CL_S_COUNT_INT-1:0] b_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0;
+
+    assign int_m_axil_bresp[n] = int_axil.bresp;
+    assign int_m_axil_buser[n] = int_axil.buser;
+
+    always_comb begin
+        int_axil_bvalid[n] = '0;
+        int_axil_bvalid[n][b_select] = int_axil.bvalid;
+    end
+    assign int_axil.bready = int_axil_bready[b_select][n];
+
+    assign fifo_rd_en = int_axil.bvalid && int_axil.bready;
+
+    // M side register
+    taxi_axil_register_wr #(
+        .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+        .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+        .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_wr(int_axil),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_wr(m_axil_wr[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect.f

@@ -0,0 +1,6 @@
+taxi_axil_interconnect.sv
+taxi_axil_interconnect_rd.sv
+taxi_axil_interconnect_wr.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_interconnect.sv

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect
+ */
+module taxi_axil_interconnect #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT],
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+taxi_axil_interconnect_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    .s_axil_wr(s_axil_wr),
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    .m_axil_wr(m_axil_wr)
+);
+
+taxi_axil_interconnect_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_SECURE(M_SECURE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    .s_axil_rd(s_axil_rd),
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    .m_axil_rd(m_axil_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect_rd.sv

@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect (read)
+ */
+module taxi_axil_interconnect_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_rd[0].DATA_W;
+localparam S_ADDR_W = s_axil_rd[0].ADDR_W;
+localparam STRB_W = s_axil_rd[0].STRB_W;
+localparam logic ARUSER_EN = s_axil_rd[0].ARUSER_EN && m_axil_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
+localparam RUSER_W = s_axil_rd[0].RUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axil_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DECODE = 2'd1,
+    STATE_READ = 2'd2,
+    STATE_WAIT_IDLE = 2'd3;
+
+logic [1:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [ADDR_W-1:0] axil_araddr_reg = '0, axil_araddr_next;
+logic axil_araddr_valid_reg = 1'b0, axil_araddr_valid_next;
+logic [2:0] axil_arprot_reg = 3'b000, axil_arprot_next;
+logic [ARUSER_W-1:0] axil_aruser_reg = '0, axil_aruser_next;
+logic [DATA_W-1:0] axil_rdata_reg = '0, axil_rdata_next;
+logic [1:0] axil_rresp_reg = 2'b00, axil_rresp_next;
+logic [RUSER_W-1:0] axil_ruser_reg = '0, axil_ruser_next;
+
+logic [S_COUNT-1:0] s_axil_arready_reg = '0, s_axil_arready_next;
+logic [S_COUNT-1:0] s_axil_rvalid_reg = '0, s_axil_rvalid_next;
+
+logic [M_COUNT-1:0] m_axil_arvalid_reg = '0, m_axil_arvalid_next;
+logic [M_COUNT-1:0] m_axil_rready_reg = '0, m_axil_rready_next;
+
+// unpack interface array
+wire [ADDR_W-1:0]    s_axil_araddr[S_COUNT];
+wire [2:0]           s_axil_arprot[S_COUNT];
+wire [ARUSER_W-1:0]  s_axil_aruser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_arvalid;
+wire [S_COUNT-1:0]   s_axil_rready;
+
+wire [M_COUNT-1:0]   m_axil_arready;
+wire [DATA_W-1:0]    m_axil_rdata[M_COUNT];
+wire [1:0]           m_axil_rresp[M_COUNT];
+wire [RUSER_W-1:0]   m_axil_ruser[M_COUNT];
+wire [M_COUNT-1:0]   m_axil_rvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axil_araddr[n] = s_axil_rd[n].araddr;
+    assign s_axil_arprot[n] = s_axil_rd[n].arprot;
+    assign s_axil_aruser[n] = s_axil_rd[n].aruser;
+    assign s_axil_arvalid[n] = s_axil_rd[n].arvalid;
+    assign s_axil_rd[n].arready = s_axil_arready_reg[n];
+    assign s_axil_rd[n].rdata = axil_rdata_reg;
+    assign s_axil_rd[n].rresp = axil_rresp_reg;
+    assign s_axil_rd[n].ruser = RUSER_EN ? axil_ruser_reg : '0;
+    assign s_axil_rd[n].rvalid = s_axil_rvalid_reg[n];
+    assign s_axil_rready[n] = s_axil_rd[n].rready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axil_rd[n].araddr = AXIL_M_ADDR_W'(axil_araddr_reg);
+    assign m_axil_rd[n].arprot = axil_arprot_reg;
+    assign m_axil_rd[n].aruser = ARUSER_EN ? axil_aruser_reg : '0;
+    assign m_axil_rd[n].arvalid = m_axil_arvalid_reg[n];
+    assign m_axil_arready[n] = m_axil_rd[n].arready;
+    assign m_axil_rdata[n] = m_axil_rd[n].rdata;
+    assign m_axil_rresp[n] = m_axil_rd[n].rresp;
+    assign m_axil_ruser[n] = m_axil_rd[n].ruser;
+    assign m_axil_rvalid[n] = m_axil_rd[n].rvalid;
+    assign m_axil_rd[n].rready = m_axil_rready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [ADDR_W-1:0]    current_s_axil_araddr  = s_axil_araddr[s_select];
+wire [2:0]           current_s_axil_arprot  = s_axil_arprot[s_select];
+wire [ARUSER_W-1:0]  current_s_axil_aruser  = s_axil_aruser[s_select];
+wire                 current_s_axil_arvalid = s_axil_arvalid[s_select];
+wire                 current_s_axil_rready  = s_axil_rready[s_select];
+
+// master side mux
+wire                 current_m_axil_arready = m_axil_arready[m_select_reg];
+wire [DATA_W-1:0]    current_m_axil_rdata   = m_axil_rdata[m_select_reg];
+wire [1:0]           current_m_axil_rresp   = m_axil_rresp[m_select_reg];
+wire [RUSER_W-1:0]   current_m_axil_ruser   = m_axil_ruser[m_select_reg];
+wire                 current_m_axil_rvalid  = m_axil_rvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+// req generation
+assign req = s_axil_arvalid;
+assign ack = grant & s_axil_rvalid_reg & s_axil_rready;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axil_araddr_next = axil_araddr_reg;
+    axil_araddr_valid_next = axil_araddr_valid_reg;
+    axil_arprot_next = axil_arprot_reg;
+    axil_aruser_next = axil_aruser_reg;
+    axil_rdata_next = axil_rdata_reg;
+    axil_rresp_next = axil_rresp_reg;
+    axil_ruser_next = axil_ruser_reg;
+
+    s_axil_arready_next = '0;
+    s_axil_rvalid_next = s_axil_rvalid_reg & ~s_axil_rready;
+
+    m_axil_arvalid_next = m_axil_arvalid_reg & ~m_axil_arready;
+    m_axil_rready_next = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+            axil_araddr_valid_next = 1'b1;
+            axil_araddr_next = current_s_axil_araddr;
+            axil_arprot_next = current_s_axil_arprot;
+            axil_aruser_next = current_s_axil_aruser;
+
+            if (grant_valid) begin
+                s_axil_arready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axil_arprot_reg[1]) && M_CONNECT_INT[i][s_select] && (axil_araddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            axil_rdata_next = '0;
+            axil_rresp_next = 2'b11;
+
+            if (match) begin
+                m_axil_rready_next[m_select_next] = 1'b1;
+                state_next = STATE_READ;
+            end else begin
+                // no match; return decode error
+                s_axil_rvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        STATE_READ: begin
+            // read state; store and forward read response
+            m_axil_rready_next[m_select_reg] = 1'b1;
+
+            if (axil_araddr_valid_reg) begin
+                m_axil_arvalid_next[m_select_reg] = 1'b1;
+            end
+            axil_araddr_valid_next = 1'b0;
+
+            if (m_axil_rready_reg != 0 && current_m_axil_rvalid) begin
+                m_axil_rready_next[m_select_reg] = 1'b0;
+                axil_rdata_next = current_m_axil_rdata;
+                axil_rresp_next = current_m_axil_rresp;
+                axil_ruser_next = current_m_axil_ruser;
+                s_axil_rvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_READ;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait until grant valid is deasserted
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_select_reg <= m_select_next;
+
+    axil_araddr_reg <= axil_araddr_next;
+    axil_araddr_valid_reg <= axil_araddr_valid_next;
+    axil_arprot_reg <= axil_arprot_next;
+    axil_aruser_reg <= axil_aruser_next;
+    axil_rdata_reg <= axil_rdata_next;
+    axil_rresp_reg <= axil_rresp_next;
+    axil_ruser_reg <= axil_ruser_next;
+
+    s_axil_arready_reg <= s_axil_arready_next;
+    s_axil_rvalid_reg <= s_axil_rvalid_next;
+
+    m_axil_arvalid_reg <= m_axil_arvalid_next;
+    m_axil_rready_reg <= m_axil_rready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axil_arready_reg <= '0;
+        s_axil_rvalid_reg <= '0;
+
+        m_axil_arvalid_reg <= '0;
+        m_axil_rready_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect_wr.sv

@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect (write)
+ */
+module taxi_axil_interconnect_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_wr[0].DATA_W;
+localparam S_ADDR_W = s_axil_wr[0].ADDR_W;
+localparam STRB_W = s_axil_wr[0].STRB_W;
+localparam logic AWUSER_EN = s_axil_wr[0].AWUSER_EN && m_axil_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axil_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axil_wr[0].WUSER_EN && m_axil_wr[0].WUSER_EN;
+localparam WUSER_W = s_axil_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
+localparam BUSER_W = s_axil_wr[0].BUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axil_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_WRITE = 3'd2,
+    STATE_WRITE_RESP = 3'd3,
+    STATE_WRITE_DROP = 3'd4,
+    STATE_WAIT_IDLE = 3'd5;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [ADDR_W-1:0] axil_awaddr_reg = '0, axil_awaddr_next;
+logic axil_awaddr_valid_reg = 1'b0, axil_awaddr_valid_next;
+logic [2:0] axil_awprot_reg = 3'b000, axil_awprot_next;
+logic [AWUSER_W-1:0] axil_awuser_reg = '0, axil_awuser_next;
+logic [DATA_W-1:0] axil_wdata_reg = '0, axil_wdata_next;
+logic [STRB_W-1:0] axil_wstrb_reg = '0, axil_wstrb_next;
+logic [WUSER_W-1:0] axil_wuser_reg = '0, axil_wuser_next;
+logic [1:0] axil_bresp_reg = 2'b00, axil_bresp_next;
+logic [BUSER_W-1:0] axil_buser_reg = '0, axil_buser_next;
+
+logic [S_COUNT-1:0] s_axil_awready_reg = '0, s_axil_awready_next;
+logic [S_COUNT-1:0] s_axil_wready_reg = '0, s_axil_wready_next;
+logic [S_COUNT-1:0] s_axil_bvalid_reg = '0, s_axil_bvalid_next;
+
+logic [M_COUNT-1:0] m_axil_awvalid_reg = '0, m_axil_awvalid_next;
+logic [M_COUNT-1:0] m_axil_wvalid_reg = '0, m_axil_wvalid_next;
+logic [M_COUNT-1:0] m_axil_bready_reg = '0, m_axil_bready_next;
+
+// unpack interface array
+wire [ADDR_W-1:0]    s_axil_awaddr[S_COUNT];
+wire [2:0]           s_axil_awprot[S_COUNT];
+wire [AWUSER_W-1:0]  s_axil_awuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_awvalid;
+wire [DATA_W-1:0]    s_axil_wdata[S_COUNT];
+wire [STRB_W-1:0]    s_axil_wstrb[S_COUNT];
+wire [WUSER_W-1:0]   s_axil_wuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_wvalid;
+wire [S_COUNT-1:0]   s_axil_bready;
+
+wire [M_COUNT-1:0]   m_axil_awready;
+wire [M_COUNT-1:0]   m_axil_wready;
+wire [1:0]           m_axil_bresp[M_COUNT];
+wire [BUSER_W-1:0]   m_axil_buser[M_COUNT];
+wire [M_COUNT-1:0]   m_axil_bvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axil_awaddr[n] = s_axil_wr[n].awaddr;
+    assign s_axil_awprot[n] = s_axil_wr[n].awprot;
+    assign s_axil_awuser[n] = s_axil_wr[n].awuser;
+    assign s_axil_awvalid[n] = s_axil_wr[n].awvalid;
+    assign s_axil_wr[n].awready = s_axil_awready_reg[n];
+    assign s_axil_wdata[n] = s_axil_wr[n].wdata;
+    assign s_axil_wstrb[n] = s_axil_wr[n].wstrb;
+    assign s_axil_wuser[n] = s_axil_wr[n].wuser;
+    assign s_axil_wvalid[n] = s_axil_wr[n].wvalid;
+    assign s_axil_wr[n].wready = s_axil_wready_reg[n];
+    assign s_axil_wr[n].bresp = axil_bresp_reg;
+    assign s_axil_wr[n].buser = BUSER_EN ? axil_buser_reg : '0;
+    assign s_axil_wr[n].bvalid = s_axil_bvalid_reg[n];
+    assign s_axil_bready[n] = s_axil_wr[n].bready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axil_wr[n].awaddr = AXIL_M_ADDR_W'(axil_awaddr_reg);
+    assign m_axil_wr[n].awprot = axil_awprot_reg;
+    assign m_axil_wr[n].awuser = AWUSER_EN ? axil_awuser_reg : '0;
+    assign m_axil_wr[n].awvalid = m_axil_awvalid_reg[n];
+    assign m_axil_awready[n] = m_axil_wr[n].awready;
+    assign m_axil_wr[n].wdata = axil_wdata_reg;
+    assign m_axil_wr[n].wstrb = axil_wstrb_reg;
+    assign m_axil_wr[n].wuser = AWUSER_EN ? axil_wuser_reg : '0;
+    assign m_axil_wr[n].wvalid = m_axil_wvalid_reg[n];
+    assign m_axil_wready[n] = m_axil_wr[n].wready;
+    assign m_axil_bresp[n] = m_axil_wr[n].bresp;
+    assign m_axil_buser[n] = m_axil_wr[n].buser;
+    assign m_axil_bvalid[n] = m_axil_wr[n].bvalid;
+    assign m_axil_wr[n].bready = m_axil_bready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [ADDR_W-1:0]    current_s_axil_awaddr  = s_axil_awaddr[s_select];
+wire [2:0]           current_s_axil_awprot  = s_axil_awprot[s_select];
+wire [AWUSER_W-1:0]  current_s_axil_awuser  = s_axil_awuser[s_select];
+wire                 current_s_axil_awvalid = s_axil_awvalid[s_select];
+wire [DATA_W-1:0]    current_s_axil_wdata   = s_axil_wdata[s_select];
+wire [STRB_W-1:0]    current_s_axil_wstrb   = s_axil_wstrb[s_select];
+wire [WUSER_W-1:0]   current_s_axil_wuser   = s_axil_wuser[s_select];
+wire                 current_s_axil_wvalid  = s_axil_wvalid[s_select];
+wire                 current_s_axil_bready  = s_axil_bready[s_select];
+
+// master side mux
+wire                 current_m_axil_awready = m_axil_awready[m_select_reg];
+wire                 current_m_axil_wready  = m_axil_wready[m_select_reg];
+wire [1:0]           current_m_axil_bresp   = m_axil_bresp[m_select_reg];
+wire [BUSER_W-1:0]   current_m_axil_buser   = m_axil_buser[m_select_reg];
+wire                 current_m_axil_bvalid  = m_axil_bvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+assign req = s_axil_awvalid;
+assign ack = grant & s_axil_bvalid_reg & s_axil_bready;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axil_awaddr_next = axil_awaddr_reg;
+    axil_awaddr_valid_next = axil_awaddr_valid_reg;
+    axil_awprot_next = axil_awprot_reg;
+    axil_awuser_next = axil_awuser_reg;
+    axil_wdata_next = axil_wdata_reg;
+    axil_wstrb_next = axil_wstrb_reg;
+    axil_wuser_next = axil_wuser_reg;
+    axil_bresp_next = axil_bresp_reg;
+    axil_buser_next = axil_buser_reg;
+
+    s_axil_awready_next = '0;
+    s_axil_wready_next = '0;
+    s_axil_bvalid_next = s_axil_bvalid_reg & ~s_axil_bready;
+
+    m_axil_awvalid_next = m_axil_awvalid_reg & ~m_axil_awready;
+    m_axil_wvalid_next = m_axil_wvalid_reg & ~m_axil_wready;
+    m_axil_bready_next = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+            axil_awaddr_valid_next = 1'b1;
+            axil_awaddr_next = current_s_axil_awaddr;
+            axil_awprot_next = current_s_axil_awprot;
+            axil_awuser_next = current_s_axil_awuser;
+
+            if (grant_valid) begin
+                s_axil_awready_next[grant_index] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axil_awprot_reg[1]) && M_CONNECT_INT[i][s_select] && (axil_awaddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            s_axil_wready_next[s_select] = 1'b1;
+
+            if (match) begin
+                state_next = STATE_WRITE;
+            end else begin
+                // no match; return decode error
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WRITE: begin
+            // write state; store and forward write data
+            s_axil_wready_next[s_select] = 1'b1;
+
+            if (axil_awaddr_valid_reg) begin
+                m_axil_awvalid_next[m_select_reg] = 1'b1;
+            end
+            axil_awaddr_valid_next = 1'b0;
+
+            axil_wdata_next = current_s_axil_wdata;
+            axil_wstrb_next = current_s_axil_wstrb;
+            axil_wuser_next = current_s_axil_wuser;
+
+            if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
+                s_axil_wready_next[s_select] = 1'b0;
+                m_axil_wvalid_next[m_select_reg] = 1'b1;
+                m_axil_bready_next[m_select_reg] = 1'b1;
+                state_next = STATE_WRITE_RESP;
+            end else begin
+                state_next = STATE_WRITE;
+            end
+        end
+        STATE_WRITE_RESP: begin
+            // write response state; store and forward write response
+            m_axil_bready_next[m_select_reg] = 1'b1;
+
+            axil_bresp_next = current_m_axil_bresp;
+            axil_buser_next = current_m_axil_buser;
+
+            if (m_axil_bready_reg != 0 && current_m_axil_bvalid) begin
+                m_axil_bready_next[m_select_reg] = 1'b0;
+                s_axil_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_RESP;
+            end
+        end
+        STATE_WRITE_DROP: begin
+            // write drop state; drop write data
+            s_axil_wready_next[s_select] = 1'b1;
+
+            axil_awaddr_valid_next = 1'b0;
+
+            axil_bresp_next = 2'b11;
+            axil_buser_next = '0;
+
+            if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
+                s_axil_wready_next[s_select] = 1'b0;
+                s_axil_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait until grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_select_reg <= m_select_next;
+
+    axil_awaddr_reg <= axil_awaddr_next;
+    axil_awaddr_valid_reg <= axil_awaddr_valid_next;
+    axil_awprot_reg <= axil_awprot_next;
+    axil_awuser_reg <= axil_awuser_next;
+    axil_wdata_reg <= axil_wdata_next;
+    axil_wstrb_reg <= axil_wstrb_next;
+    axil_wuser_reg <= axil_wuser_next;
+    axil_bresp_reg <= axil_bresp_next;
+    axil_buser_reg <= axil_buser_next;
+
+    s_axil_awready_reg <= s_axil_awready_next;
+    s_axil_wready_reg <= s_axil_wready_next;
+    s_axil_bvalid_reg <= s_axil_bvalid_next;
+
+    m_axil_awvalid_reg <= m_axil_awvalid_next;
+    m_axil_wvalid_reg <= m_axil_wvalid_next;
+    m_axil_bready_reg <= m_axil_bready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axil_awready_reg <= '0;
+        s_axil_wready_reg <= '0;
+        s_axil_bvalid_reg <= '0;
+
+        m_axil_awvalid_reg <= '0;
+        m_axil_wvalid_reg <= '0;
+        m_axil_bready_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axi_crossbar/Makefile

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axi_crossbar
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_S_ID_W := 8
+export PARAM_M_ID_W := $(shell expr $(PARAM_S_ID_W) + 2 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.py

@@ -0,0 +1,281 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axi_master = [AxiMaster(AxiBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axi]
+        self.axi_ram = [AxiRam(AxiBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axi]
+
+        for ram in self.axi_ram:
+            # prevent X propagation from screwing things up - "anything but X!"
+            # (X on bid and rid can propagate X to ready/valid)
+            ram.write_if.b_channel.bus.bid.setimmediatevalue(0)
+            ram.read_if.r_channel.bus.rid.setimmediatevalue(0)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axi_master[s].write(addr, test_data, size=size)
+
+            tb.log.debug("%s", tb.axi_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axi_ram[m].read(ram_addr, length) == test_data
+            assert tb.axi_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axi_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axi_master[s].read(addr, length, size=size)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axi_ram))
+            length = random.randint(1, min(512, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axi)
+    m_count = len(cocotb.top.m_axi)
+
+    data_w = len(cocotb.top.s_axi[0].wdata)
+    byte_lanes = data_w // 8
+    max_burst_size = (byte_lanes-1).bit_length()
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        # factory.add_option("size", [None]+list(range(max_burst_size)))
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axi_crossbar(request, s_count, m_count, data_w):
+    dut = "taxi_axi_crossbar"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['S_ID_W'] = 8
+    parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.sv

@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar testbench
+ */
+module test_taxi_axi_crossbar #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter S_ID_W = 8,
+    parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(S_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axi[S_COUNT]();
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(M_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axi[M_COUNT]();
+
+taxi_axi_crossbar #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE),
+    .M_AW_REG_TYPE(M_AW_REG_TYPE),
+    .M_W_REG_TYPE(M_W_REG_TYPE),
+    .M_B_REG_TYPE(M_B_REG_TYPE),
+    .M_AR_REG_TYPE(M_AR_REG_TYPE),
+    .M_R_REG_TYPE(M_R_REG_TYPE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interface
+     */
+    .s_axi_wr(s_axi),
+    .s_axi_rd(s_axi),
+
+    /*
+     * AXI4 master interface
+     */
+    .m_axi_wr(m_axi),
+    .m_axi_rd(m_axi)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axi_interconnect/Makefile

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axi_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_S_ID_W := 8
+export PARAM_M_ID_W := $(shell expr $(PARAM_S_ID_W) + 2 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.py

@@ -0,0 +1,275 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axi_master = [AxiMaster(AxiBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axi]
+        self.axi_ram = [AxiRam(AxiBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axi]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axi_master[s].write(addr, test_data, size=size)
+
+            tb.log.debug("%s", tb.axi_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axi_ram[m].read(ram_addr, length) == test_data
+            assert tb.axi_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axi_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axi_master[s].read(addr, length, size=size)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axi_ram))
+            length = random.randint(1, min(512, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axi)
+    m_count = len(cocotb.top.m_axi)
+
+    data_w = len(cocotb.top.s_axi[0].wdata)
+    byte_lanes = data_w // 8
+    max_burst_size = (byte_lanes-1).bit_length()
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        # factory.add_option("size", [None]+list(range(max_burst_size)))
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axi_interconnect(request, s_count, m_count, data_w):
+    dut = "taxi_axi_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['S_ID_W'] = 8
+    parameters['M_ID_W'] = parameters['S_ID_W']
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect testbench
+ */
+module test_taxi_axi_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter S_ID_W = 8,
+    parameter M_ID_W = S_ID_W,
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_SECURE = {M_COUNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(S_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axi[S_COUNT]();
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(M_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axi[M_COUNT]();
+
+taxi_axi_interconnect #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interface
+     */
+    .s_axi_wr(s_axi),
+    .s_axi_rd(s_axi),
+
+    /*
+     * AXI4 master interface
+     */
+    .m_axi_wr(m_axi),
+    .m_axi_rd(m_axi)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axil_crossbar/Makefile

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axil_crossbar
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.py

@@ -0,0 +1,260 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axil_master = [AxiLiteMaster(AxiLiteBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axil]
+        self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axil_master[s].write(addr, test_data)
+
+            tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram[m].read(ram_addr, length) == test_data
+            assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axil_master[s].read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axil_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axil)
+    m_count = len(cocotb.top.m_axil)
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axil_crossbar(request, s_count, m_count, data_w):
+    dut = "taxi_axil_crossbar"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv

@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-lite crossbar testbench
+ */
+module test_taxi_axil_crossbar #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axil[S_COUNT]();
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axil[M_COUNT]();
+
+taxi_axil_crossbar #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE),
+    .M_AW_REG_TYPE(M_AW_REG_TYPE),
+    .M_W_REG_TYPE(M_W_REG_TYPE),
+    .M_B_REG_TYPE(M_B_REG_TYPE),
+    .M_AR_REG_TYPE(M_AR_REG_TYPE),
+    .M_R_REG_TYPE(M_R_REG_TYPE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interface
+     */
+    .s_axil_wr(s_axil),
+    .s_axil_rd(s_axil),
+
+    /*
+     * AXI4-lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axil_interconnect/Makefile

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axil_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.py

@@ -0,0 +1,260 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axil_master = [AxiLiteMaster(AxiLiteBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axil]
+        self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axil_master[s].write(addr, test_data)
+
+            tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram[m].read(ram_addr, length) == test_data
+            assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axil_master[s].read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axil_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axil)
+    m_count = len(cocotb.top.m_axil)
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axil_interconnect(request, s_count, m_count, data_w):
+    dut = "taxi_axil_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.sv

@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-lite interconnect testbench
+ */
+module test_taxi_axil_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_SECURE = {M_COUNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axil[S_COUNT]();
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axil[M_COUNT]();
+
+taxi_axil_interconnect #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interface
+     */
+    .s_axil_wr(s_axil),
+    .s_axil_rd(s_axil),
+
+    /*
+     * AXI4-lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall

src/axis/rtl/taxi_axis_async_fifo.sv

@@ -142,6 +142,12 @@ if (m_axis.DATA_W != DATA_W)
 if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
     $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
 
+if (DROP_BAD_FRAME && !s_axis.USER_EN)
+    $fatal(0, "Error: DROP_BAD_FRAME set requires s_axis.USER_EN (instance %m)");
+
+if (MARK_WHEN_FULL && !m_axis.USER_EN)
+    $fatal(0, "Error: MARK_WHEN_FULL set requires m_axis.USER_EN (instance %m)");
+
 localparam KEEP_OFFSET = DATA_W;
 localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
 localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
@@ -645,7 +651,7 @@ always_ff @(posedge m_clk) begin
             mem_rd_valid_pipe_reg[0] <= 1'b1;
             rd_ptr_temp = rd_ptr_reg + 1;
             rd_ptr_reg <= rd_ptr_temp;
-            rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
+            rd_ptr_gray_reg <= bin2gray(rd_ptr_temp);;
         end
     end
 

src/axis/rtl/taxi_axis_broadcast.sv

@@ -105,7 +105,7 @@ end
 // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
 wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid));
 
-always @* begin
+always_comb begin
     // transfer sink ready state to source
     m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
     temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
@@ -133,7 +133,7 @@ always @* begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     s_axis_tready_reg <= s_axis_tready_early;
     m_axis_tvalid_reg <= m_axis_tvalid_next;
     temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;

src/axis/rtl/taxi_axis_cobs_encode.sv

@@ -141,7 +141,7 @@ data_fifo_inst (
     .status_good_frame()
 );
 
-always @* begin
+always_comb begin
     input_state_next = INPUT_STATE_IDLE;
 
     input_count_next = input_count_reg;
@@ -304,7 +304,7 @@ always @* begin
     endcase
 end
 
-always @* begin
+always_comb begin
     output_state_next = OUTPUT_STATE_IDLE;
 
     output_count_next = output_count_reg;
@@ -365,7 +365,7 @@ always @* begin
     endcase
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     input_state_reg <= input_state_next;
     output_state_reg <= output_state_next;
 
@@ -380,20 +380,20 @@ always @(posedge clk) begin
 end
 
 // output datapath logic
-reg [7:0] m_axis_tdata_reg = 8'd0;
-reg       m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
-reg       m_axis_tlast_reg = 1'b0;
-reg       m_axis_tuser_reg = 1'b0;
+logic [7:0] m_axis_tdata_reg = 8'd0;
+logic       m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+logic       m_axis_tlast_reg = 1'b0;
+logic       m_axis_tuser_reg = 1'b0;
 
-reg [7:0] temp_m_axis_tdata_reg = 8'd0;
-reg       temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
-reg       temp_m_axis_tlast_reg = 1'b0;
-reg       temp_m_axis_tuser_reg = 1'b0;
+logic [7:0] temp_m_axis_tdata_reg = 8'd0;
+logic       temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+logic       temp_m_axis_tlast_reg = 1'b0;
+logic       temp_m_axis_tuser_reg = 1'b0;
 
 // datapath control
-reg store_axis_int_to_output;
-reg store_axis_int_to_temp;
-reg store_axis_temp_to_output;
+logic store_axis_int_to_output;
+logic store_axis_int_to_temp;
+logic store_axis_temp_to_output;
 
 assign m_axis.tdata = m_axis_tdata_reg;
 assign m_axis.tkeep = 1'b1;
@@ -407,7 +407,7 @@ assign m_axis.tuser = m_axis_tuser_reg;
 // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
 assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
 
-always @* begin
+always_comb begin
     // transfer sink ready state to source
     m_axis_tvalid_next = m_axis_tvalid_reg;
     temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
@@ -435,7 +435,7 @@ always @* begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     m_axis_tvalid_reg <= m_axis_tvalid_next;
     m_axis_tready_int_reg <= m_axis_tready_int_early;
     temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;

src/axis/rtl/taxi_axis_concat.sv

@@ -123,7 +123,7 @@ end else begin
     // destripe
     logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
 
-    reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
+    logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
 
     assign s_axis_tready = s_axis_tready_reg;
 

src/axis/rtl/taxi_axis_fifo.sv

@@ -130,10 +130,16 @@ if (m_axis.DATA_W != DATA_W)
 if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
     $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
 
+if (DROP_BAD_FRAME && !s_axis.USER_EN)
+    $fatal(0, "Error: DROP_BAD_FRAME set requires s_axis.USER_EN (instance %m)");
+
+if (MARK_WHEN_FULL && !m_axis.USER_EN)
+    $fatal(0, "Error: MARK_WHEN_FULL set requires m_axis.USER_EN (instance %m)");
+
 localparam KEEP_OFFSET = DATA_W;
 localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
 localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
-localparam ID_OFFSET   = LAST_OFFSET + (LAST_EN ? 1          : 0);
+localparam ID_OFFSET   = LAST_OFFSET + (LAST_EN ? 1      : 0);
 localparam DEST_OFFSET = ID_OFFSET   + (ID_EN   ? ID_W   : 0);
 localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
 localparam WIDTH       = USER_OFFSET + (USER_EN ? USER_W : 0);

src/axis/rtl/taxi_axis_mux.sv

@@ -63,21 +63,21 @@ if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
 
 parameter CL_S_COUNT = $clog2(S_COUNT);
 
-reg [CL_S_COUNT-1:0] select_reg = '0, select_next;
-reg frame_reg = 1'b0, frame_next;
+logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
+logic frame_reg = 1'b0, frame_next;
 
-reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
+logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
 
 // internal datapath
-reg  [DATA_W-1:0]  m_axis_tdata_int;
-reg  [KEEP_W-1:0]  m_axis_tkeep_int;
-reg  [KEEP_W-1:0]  m_axis_tstrb_int;
-reg                m_axis_tvalid_int;
-reg                m_axis_tready_int_reg = 1'b0;
-reg                m_axis_tlast_int;
-reg  [ID_W-1:0]    m_axis_tid_int;
-reg  [DEST_W-1:0]  m_axis_tdest_int;
-reg  [USER_W-1:0]  m_axis_tuser_int;
+logic  [DATA_W-1:0]  m_axis_tdata_int;
+logic  [KEEP_W-1:0]  m_axis_tkeep_int;
+logic  [KEEP_W-1:0]  m_axis_tstrb_int;
+logic                m_axis_tvalid_int;
+logic                m_axis_tready_int_reg = 1'b0;
+logic                m_axis_tlast_int;
+logic  [ID_W-1:0]    m_axis_tid_int;
+logic  [DEST_W-1:0]  m_axis_tdest_int;
+logic  [USER_W-1:0]  m_axis_tuser_int;
 wire               m_axis_tready_int_early;
 
 // unpack interface array
@@ -162,28 +162,28 @@ always_ff @(posedge clk) begin
 end
 
 // output datapath logic
-reg [DATA_W-1:0]  m_axis_tdata_reg  = '0;
-reg [KEEP_W-1:0]  m_axis_tkeep_reg  = '0;
-reg [KEEP_W-1:0]  m_axis_tstrb_reg  = '0;
-reg               m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
-reg               m_axis_tlast_reg  = 1'b0;
-reg [ID_W-1:0]    m_axis_tid_reg    = '0;
-reg [DEST_W-1:0]  m_axis_tdest_reg  = '0;
-reg [USER_W-1:0]  m_axis_tuser_reg  = '0;
+logic [DATA_W-1:0]  m_axis_tdata_reg  = '0;
+logic [KEEP_W-1:0]  m_axis_tkeep_reg  = '0;
+logic [KEEP_W-1:0]  m_axis_tstrb_reg  = '0;
+logic               m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+logic               m_axis_tlast_reg  = 1'b0;
+logic [ID_W-1:0]    m_axis_tid_reg    = '0;
+logic [DEST_W-1:0]  m_axis_tdest_reg  = '0;
+logic [USER_W-1:0]  m_axis_tuser_reg  = '0;
 
-reg [DATA_W-1:0]  temp_m_axis_tdata_reg  = '0;
-reg [KEEP_W-1:0]  temp_m_axis_tkeep_reg  = '0;
-reg [KEEP_W-1:0]  temp_m_axis_tstrb_reg  = '0;
-reg               temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
-reg               temp_m_axis_tlast_reg  = 1'b0;
-reg [ID_W-1:0]    temp_m_axis_tid_reg    = '0;
-reg [DEST_W-1:0]  temp_m_axis_tdest_reg  = '0;
-reg [USER_W-1:0]  temp_m_axis_tuser_reg  = '0;
+logic [DATA_W-1:0]  temp_m_axis_tdata_reg  = '0;
+logic [KEEP_W-1:0]  temp_m_axis_tkeep_reg  = '0;
+logic [KEEP_W-1:0]  temp_m_axis_tstrb_reg  = '0;
+logic               temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+logic               temp_m_axis_tlast_reg  = 1'b0;
+logic [ID_W-1:0]    temp_m_axis_tid_reg    = '0;
+logic [DEST_W-1:0]  temp_m_axis_tdest_reg  = '0;
+logic [USER_W-1:0]  temp_m_axis_tuser_reg  = '0;
 
 // datapath control
-reg store_axis_int_to_output;
-reg store_axis_int_to_temp;
-reg store_axis_temp_to_output;
+logic store_axis_int_to_output;
+logic store_axis_int_to_temp;
+logic store_axis_temp_to_output;
 
 assign m_axis.tdata  = m_axis_tdata_reg;
 assign m_axis.tkeep  = KEEP_EN ? m_axis_tkeep_reg : '1;

src/dma/rtl/taxi_dma_client_axis_sink.sv

@@ -418,7 +418,7 @@ always_comb begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     state_reg <= state_next;
 
     desc_req_ready_reg <= desc_req_ready_next;
@@ -484,27 +484,27 @@ end
 // output datapath logic (write data)
 for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin
 
-    reg [RAM_SEG_BE_W-1:0]   ram_wr_cmd_be_reg = '0;
-    reg [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0;
-    reg [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0;
-    reg                      ram_wr_cmd_valid_reg = 1'b0;
+    logic [RAM_SEG_BE_W-1:0]   ram_wr_cmd_be_reg = '0;
+    logic [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0;
+    logic [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0;
+    logic                      ram_wr_cmd_valid_reg = 1'b0;
 
-    reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
-    reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
-    reg out_fifo_half_full_reg = 1'b0;
+    logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
+    logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
+    logic out_fifo_half_full_reg = 1'b0;
 
     wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_BE_W-1:0]   out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_BE_W-1:0]   out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW];
 
-    reg [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0;
-    reg done_reg = 1'b0;
+    logic [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0;
+    logic done_reg = 1'b0;
 
     assign ram_wr_cmd_ready_int[n] = !out_fifo_half_full_reg;
 
@@ -515,7 +515,7 @@ for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin
 
     assign out_done[n] = done_reg;
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_reg && !dma_ram_wr.wr_cmd_ready[n];
 
         out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);

src/dma/rtl/taxi_dma_if_pcie_us_rd.sv

@@ -1537,7 +1537,7 @@ always_comb begin
     end
 end
 
-reg [1:0] active_tx_count_ovf;
+logic [1:0] active_tx_count_ovf;
 
 always_comb begin
     {active_tx_count_ovf, active_tx_count_next} = $signed({1'b0, active_tx_count_reg}) + $signed({1'b0, inc_active_tx});

src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -89,9 +89,9 @@ wire qsfp_0_mgt_refclk_bufg;
 
 wire qsfp_rst;
 
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_tx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[8]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_rx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_rx[8]();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2]();
 
 if (SIM) begin
@@ -150,6 +150,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
 
     localparam CNT = 4;
 
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
     taxi_eth_mac_25g_us #(
         .SIM(SIM),
         .VENDOR(VENDOR),
@@ -182,6 +188,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
         .xcvr_ctrl_clk(clk_125mhz),
         .xcvr_ctrl_rst(qsfp_rst),
 
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
         /*
          * Common
          */

src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv

@@ -105,9 +105,9 @@ assign sfp_mgt_refclk_out = sfp_mgt_refclk_bufg;
 
 wire sfp_rst;
 
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_tx[2]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_rx[2]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2]();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
 if (SIM) begin
@@ -147,6 +147,12 @@ sfp_sync_reset_inst (
     .out(sfp_rst)
 );
 
+taxi_apb_if #(
+    .ADDR_W(18),
+    .DATA_W(16)
+)
+gt_apb_ctrl();
+
 taxi_eth_mac_25g_us #(
     .SIM(SIM),
     .VENDOR(VENDOR),
@@ -183,6 +189,11 @@ sfp_mac_inst (
     .xcvr_ctrl_clk(clk_125mhz),
     .xcvr_ctrl_rst(sfp_rst),
 
+    /*
+     * Transceiver control
+     */
+    .s_apb_ctrl(gt_apb_ctrl),
+
     /*
      * Common
      */

src/eth/example/Alveo/fpga/fpga_AU200/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU250/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU280/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU45N/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU50/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU55C/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU55N/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_X3522/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -109,7 +109,9 @@ xfcp_if_uart_inst (
     .prescale(16'(125000000/3000000))
 );
 
-taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
+localparam XFCP_PORTS = 1+GTY_QUAD_CNT;
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
 
 taxi_xfcp_switch #(
     .XFCP_ID_STR("Alveo"),
@@ -231,12 +233,12 @@ assign eth_port_lpmode = '0;
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 
@@ -300,6 +302,31 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
     localparam CLK = n;
     localparam CNT = 4;
 
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_xfcp_mod_apb #(
+        .XFCP_EXT_ID_STR("GTY CTRL")
+    )
+    xfcp_mod_apb_inst (
+        .clk(clk_125mhz),
+        .rst(rst_125mhz),
+
+        /*
+         * XFCP upstream port
+         */
+        .xfcp_usp_ds(xfcp_sw_ds[n+1]),
+        .xfcp_usp_us(xfcp_sw_us[n+1]),
+
+        /*
+         * APB master interface
+         */
+        .m_apb(gt_apb_ctrl)
+    );
+
     taxi_eth_mac_25g_us #(
         .SIM(SIM),
         .VENDOR(VENDOR),
@@ -338,6 +365,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
         .xcvr_ctrl_clk(clk_125mhz),
         .xcvr_ctrl_rst(eth_gty_rst[CLK]),
 
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
         /*
          * Common
          */

src/eth/example/Alveo/fpga/tb/fpga_core/Makefile

@@ -26,6 +26,7 @@ VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv

src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -214,6 +214,7 @@ def test_fpga_core(request):
         os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
         os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),

src/eth/example/Arty/fpga/rtl/fpga_core.sv

@@ -157,7 +157,7 @@ xfcp_stats_inst (
     .s_axis_stat(axis_mac_stat)
 );
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 taxi_eth_mac_mii_fifo #(

src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/rtl/fpga_core.sv

@@ -198,7 +198,9 @@ xfcp_if_uart_inst (
     .prescale(16'(125000000/921600))
 );
 
-taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2]();
+localparam XFCP_PORTS = 2+GTY_QUAD_CNT;
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
 
 taxi_xfcp_switch #(
     .XFCP_ID_STR("HTG-9200"),
@@ -299,12 +301,12 @@ assign eth_port_resetl = {PORT_CNT{~eth_reset}};
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 
@@ -381,6 +383,31 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
     localparam CLK = n;
     localparam CNT = 4;
 
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_xfcp_mod_apb #(
+        .XFCP_EXT_ID_STR("GTY CTRL")
+    )
+    xfcp_mod_apb_inst (
+        .clk(clk_125mhz),
+        .rst(rst_125mhz),
+
+        /*
+         * XFCP upstream port
+         */
+        .xfcp_usp_ds(xfcp_sw_ds[n+2]),
+        .xfcp_usp_us(xfcp_sw_us[n+2]),
+
+        /*
+         * APB master interface
+         */
+        .m_apb(gt_apb_ctrl)
+    );
+
     taxi_eth_mac_25g_us #(
         .SIM(SIM),
         .VENDOR(VENDOR),
@@ -435,6 +462,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
         .xcvr_ctrl_clk(clk_125mhz),
         .xcvr_ctrl_rst(eth_gty_rst[CLK]),
 
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
         /*
          * Common
          */

src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile

@@ -27,8 +27,9 @@ VERILOG_SOURCES += $(RTL_DIR)/../pll/si5341_i2c_init.sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py

@@ -220,8 +220,9 @@ def test_fpga_core(request, mac_data_w):
         os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
-        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
         os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),

src/eth/example/HTG940/fpga/rtl/fpga_core.sv

@@ -147,7 +147,7 @@ xfcp_stats_inst (
 );
 
 // BASE-T PHY
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 taxi_eth_mac_1g_rgmii_fifo #(

src/eth/example/HTG_ZRF8/fpga/fpga_10g_EM_ZU48DR/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_em.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG_ZRF8/fpga/fpga_10g_R2_ZU48DR/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_r2.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG_ZRF8/fpga/fpga_EM_ZU48DR/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_em.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG_ZRF8/fpga/fpga_R2_ZU48DR/Makefile

@@ -22,8 +22,9 @@ SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_r2.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv

@@ -131,7 +131,9 @@ xfcp_if_uart_inst (
     .prescale(16'(125000000/921600))
 );
 
-taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[3](), xfcp_sw_us[3]();
+localparam XFCP_PORTS = 3+GTY_QUAD_CNT;
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
 
 taxi_xfcp_switch #(
     .XFCP_ID_STR("HTG-ZRF8"),
@@ -256,12 +258,12 @@ assign eth_port_resetl = {PORT_CNT{~eth_reset}};
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 
@@ -325,6 +327,31 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
     localparam CLK = n;
     localparam CNT = 4;
 
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_xfcp_mod_apb #(
+        .XFCP_EXT_ID_STR("GTY CTRL")
+    )
+    xfcp_mod_apb_inst (
+        .clk(clk_125mhz),
+        .rst(rst_125mhz),
+
+        /*
+         * XFCP upstream port
+         */
+        .xfcp_usp_ds(xfcp_sw_ds[n+3]),
+        .xfcp_usp_us(xfcp_sw_us[n+3]),
+
+        /*
+         * APB master interface
+         */
+        .m_apb(gt_apb_ctrl)
+    );
+
     taxi_eth_mac_25g_us #(
         .SIM(SIM),
         .VENDOR(VENDOR),
@@ -366,6 +393,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
         .xcvr_ctrl_clk(clk_125mhz),
         .xcvr_ctrl_rst(eth_gty_rst[CLK]),
 
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
         /*
          * Common
          */

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/Makefile

@@ -27,8 +27,9 @@ VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
-VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py

@@ -226,8 +226,9 @@ def test_fpga_core(request, mac_data_w):
         os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
-        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
         os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),

src/eth/example/KC705/fpga/fpga.xdc

@@ -80,8 +80,9 @@ set_false_path -from [get_ports {uart_rxd uart_rts}]
 set_input_delay 0 [get_ports {uart_rxd uart_rts}]
 
 # I2C interface
-#set_property -dict {LOC K21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
-#set_property -dict {LOC L21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC K21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC L21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC P23  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
 
 #set_false_path -to [get_ports {i2c_sda i2c_scl}]
 #set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
@@ -139,17 +140,28 @@ set_property -dict {LOC H6   } [get_ports phy_sgmii_rx_p] ;# MGTXRXP1_117 GTXE2_
 set_property -dict {LOC H5   } [get_ports phy_sgmii_rx_n] ;# MGTXRXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A8 SOUT_N
 set_property -dict {LOC J4   } [get_ports phy_sgmii_tx_p] ;# MGTXTXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A3 SIN_P
 set_property -dict {LOC J3   } [get_ports phy_sgmii_tx_n] ;# MGTXTXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A4 SIN_N
-set_property -dict {LOC G8   } [get_ports sgmii_clk_p] ;# MGTREFCLK0P_117 from U2.7
-set_property -dict {LOC G7   } [get_ports sgmii_clk_n] ;# MGTREFCLK0N_117 from U2.6
-#set_property -dict {LOC L8   } [get_ports sfp_clk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
-#set_property -dict {LOC L7   } [get_ports sfp_clk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
+set_property -dict {LOC G8   } [get_ports sgmii_mgt_refclk_p] ;# MGTREFCLK0P_117 from U2.7
+set_property -dict {LOC G7   } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117 from U2.6
+#set_property -dict {LOC L8   } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
+#set_property -dict {LOC L7   } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
 #set_property -dict {LOC W27 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to Si5324 U70.16 CKIN1_P
 #set_property -dict {LOC W28 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to Si5324 U70.17 CKIN1_N
 
+#set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
+#set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
+
 set_property -dict {LOC Y20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
 
-create_clock -period 8.000 -name sgmii_clk [get_ports sgmii_clk_p]
-#create_clock -period 6.400 -name sgmii_clk [get_ports sfp_clk_p]
+# 125 MHz MGT reference clock (SGMII, 1000BASE-X)
+#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]
+
+# 156.25 MHz MGT reference clock (10GBASE-R)
+#create_clock -period 6.400 -name sgmii_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+#set_false_path -to [get_ports {si5324_rst}]
+#set_output_delay 0 [get_ports {si5324_rst}]
+#set_false_path -from [get_ports {si5324_int}]
+#set_input_delay 0 [get_ports {si5324_int}]
 
 set_false_path -to [get_ports {sfp_tx_disable_b}]
 set_output_delay 0 [get_ports {sfp_tx_disable_b}]