bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 00:28:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

axi: Clean up address width handling in interconnect modules

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-12 22:01:45 -08:00
parent dd4c639600
commit 8c3709d917
10 changed files with 36 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/axi/rtl/taxi_axi_crossbar_addr.sv
View File

@@ -112,12 +112,12 @@ localparam CL_S_ACCEPT = $clog2(S_ACCEPT);
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);

4
src/axi/rtl/taxi_axi_crossbar_rd.sv
View File

@@ -87,6 +87,8 @@ localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
localparam RUSER_W = s_axi_rd[0].RUSER_W;
localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -451,7 +453,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
end else begin
assign int_axi.arid = int_s_axi_arid[a_grant_index];
end
assign int_axi.araddr = int_s_axi_araddr[a_grant_index];
assign int_axi.araddr = AXI_M_ADDR_W'(int_s_axi_araddr[a_grant_index]);
assign int_axi.arlen = int_s_axi_arlen[a_grant_index];
assign int_axi.arsize = int_s_axi_arsize[a_grant_index];
assign int_axi.arburst = int_s_axi_arburst[a_grant_index];

4
src/axi/rtl/taxi_axi_crossbar_wr.sv
View File

@@ -95,6 +95,8 @@ localparam WUSER_W = s_axi_wr[0].WUSER_W;
localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
localparam BUSER_W = s_axi_wr[0].BUSER_W;
localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -502,7 +504,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
end else begin
assign int_axi.awid = int_s_axi_awid[a_grant_index];
end
assign int_axi.awaddr = int_s_axi_awaddr[a_grant_index];
assign int_axi.awaddr = AXI_M_ADDR_W'(int_s_axi_awaddr[a_grant_index]);
assign int_axi.awlen = int_s_axi_awlen[a_grant_index];
assign int_axi.awsize = int_s_axi_awsize[a_grant_index];
assign int_axi.awburst = int_s_axi_awburst[a_grant_index];

8
src/axi/rtl/taxi_axi_interconnect_rd.sv
View File

@@ -66,6 +66,8 @@ localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
localparam RUSER_W = s_axi_rd[0].RUSER_W;
localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -78,12 +80,12 @@ localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
@@ -258,7 +260,7 @@ end
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
assign m_axi_rd[n].arid = axi_id_reg;
assign m_axi_rd[n].araddr = axi_addr_reg;
assign m_axi_rd[n].araddr = AXI_M_ADDR_W'(axi_addr_reg);
assign m_axi_rd[n].arlen = axi_len_reg;
assign m_axi_rd[n].arsize = axi_size_reg;
assign m_axi_rd[n].arburst = axi_burst_reg;

8
src/axi/rtl/taxi_axi_interconnect_wr.sv
View File

@@ -68,6 +68,8 @@ localparam WUSER_W = s_axi_wr[0].WUSER_W;
localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
localparam BUSER_W = s_axi_wr[0].BUSER_W;
localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -80,12 +82,12 @@ localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
@@ -281,7 +283,7 @@ end
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
assign m_axi_wr[n].awid = axi_id_reg;
assign m_axi_wr[n].awaddr = axi_addr_reg;
assign m_axi_wr[n].awaddr = AXI_M_ADDR_W'(axi_addr_reg);
assign m_axi_wr[n].awlen = axi_len_reg;
assign m_axi_wr[n].awsize = axi_size_reg;
assign m_axi_wr[n].awburst = axi_burst_reg;

4
src/axi/rtl/taxi_axil_crossbar_addr.sv
View File

@@ -96,12 +96,12 @@ localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);

4
src/axi/rtl/taxi_axil_crossbar_rd.sv
View File

@@ -82,6 +82,8 @@ localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
localparam RUSER_W = s_axil_rd[0].RUSER_W;
localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -397,7 +399,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
end
// address mux
assign int_axil.araddr = int_s_axil_araddr[a_grant_index];
assign int_axil.araddr = AXIL_M_ADDR_W'(int_s_axil_araddr[a_grant_index]);
assign int_axil.arprot = int_s_axil_arprot[a_grant_index];
assign int_axil.aruser = int_s_axil_aruser[a_grant_index];
assign int_axil.arvalid = int_axil_arvalid[a_grant_index][n] && a_grant_valid;

4
src/axi/rtl/taxi_axil_crossbar_wr.sv
View File

@@ -90,6 +90,8 @@ localparam WUSER_W = s_axil_wr[0].WUSER_W;
localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
localparam BUSER_W = s_axil_wr[0].BUSER_W;
localparam AXIL_M_ADDR_W = m_axil_wr[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -462,7 +464,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
end
// address mux
assign int_axil.awaddr = int_s_axil_awaddr[a_grant_index];
assign int_axil.awaddr = AXIL_M_ADDR_W'(int_s_axil_awaddr[a_grant_index]);
assign int_axil.awprot = int_s_axil_awprot[a_grant_index];
assign int_axil.awuser = int_s_axil_awuser[a_grant_index];
assign int_axil.awvalid = int_axil_awvalid[a_grant_index][n] && a_grant_valid;

8
src/axi/rtl/taxi_axil_interconnect_rd.sv
View File

@@ -64,6 +64,8 @@ localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
localparam RUSER_W = s_axil_rd[0].RUSER_W;
localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -76,12 +78,12 @@ localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
@@ -227,7 +229,7 @@ for (genvar n = 0; n < S_COUNT; n = n + 1) begin
end
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
assign m_axil_rd[n].araddr = axil_araddr_reg;
assign m_axil_rd[n].araddr = AXIL_M_ADDR_W'(axil_addr_reg);
assign m_axil_rd[n].arprot = axil_arprot_reg;
assign m_axil_rd[n].aruser = ARUSER_EN ? axil_aruser_reg : '0;
assign m_axil_rd[n].arvalid = m_axil_arvalid_reg[n];

8
src/axi/rtl/taxi_axil_interconnect_wr.sv
View File

@@ -66,6 +66,8 @@ localparam WUSER_W = s_axil_wr[0].WUSER_W;
localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
localparam BUSER_W = s_axil_wr[0].BUSER_W;
localparam AXIL_M_ADDR_W = m_axi_wr[0].ADDR_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam CL_M_COUNT = $clog2(M_COUNT);
localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
@@ -78,12 +80,12 @@ localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
// default address computation
function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
logic [ADDR_W-1:0] base;
logic [ADDR_W-1:0] width;
integer width;
logic [ADDR_W-1:0] size;
logic [ADDR_W-1:0] mask;
begin
calcBaseAddrs = '0;
base = 0;
base = '0;
for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
width = M_ADDR_W_INT[i];
mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
@@ -243,7 +245,7 @@ for (genvar n = 0; n < S_COUNT; n = n + 1) begin
end
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
assign m_axil_wr[n].awaddr = axil_awaddr_reg;
assign m_axil_wr[n].awaddr = AXIL_M_ADDR_W'(axil_awaddr_reg);
assign m_axil_wr[n].awprot = axil_awprot_reg;
assign m_axil_wr[n].awuser = AWUSER_EN ? axil_awuser_reg : '0;
assign m_axil_wr[n].awvalid = m_axil_awvalid_reg[n];