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https://github.com/fpganinja/taxi.git
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669 lines
24 KiB
Systemverilog
669 lines
24 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 interconnect
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*/
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module taxi_axi_interconnect_wr #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 4,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = 0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Write connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interfaces
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*/
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taxi_axi_if.wr_slv s_axi_wr[S_COUNT],
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/*
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* AXI4 master interfaces
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*/
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taxi_axi_if.wr_mst m_axi_wr[M_COUNT]
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);
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// extract parameters
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localparam DATA_W = s_axi_wr[0].DATA_W;
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localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
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localparam STRB_W = s_axi_wr[0].STRB_W;
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localparam S_ID_W = s_axi_wr[0].ID_W;
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localparam M_ID_W = m_axi_wr[0].ID_W;
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localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
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localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
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localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
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localparam WUSER_W = s_axi_wr[0].WUSER_W;
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localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
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localparam BUSER_W = s_axi_wr[0].BUSER_W;
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localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
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localparam CL_S_COUNT = $clog2(S_COUNT);
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localparam CL_M_COUNT = $clog2(M_COUNT);
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localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
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localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
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localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
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localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
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localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
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// default address computation
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function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
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logic [ADDR_W-1:0] base;
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integer width;
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logic [ADDR_W-1:0] size;
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logic [ADDR_W-1:0] mask;
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begin
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calcBaseAddrs = '0;
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base = '0;
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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width = M_ADDR_W_INT[i];
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mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
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size = mask + 1;
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if (width > 0) begin
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if ((base & mask) != 0) begin
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base = base + size - (base & mask); // align
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end
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calcBaseAddrs[i] = base;
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base = base + size; // increment
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end
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end
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end
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endfunction
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localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
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// check configuration
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if (s_axi_wr[0].ADDR_W != ADDR_W)
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$fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
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if (m_axi_wr[0].DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axi_wr[0].STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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initial begin
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if (M_REGIONS < 1 || M_REGIONS > 16) begin
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$error("Error: M_REGIONS must be between 1 and 16 (instance %m)");
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$finish;
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end
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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/* verilator lint_off UNSIGNED */
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if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
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$error("Error: address width out of range (instance %m)");
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$finish;
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end
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/* verilator lint_on UNSIGNED */
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end
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$display("Addressing configuration for axi_interconnect instance %m");
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if (M_ADDR_W_INT[i] != 0) begin
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$display("%2d (%2d): %x / %02d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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end
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end
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
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$display("Region not aligned:");
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$display("%2d (%2d): %x / %2d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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$error("Error: address range not aligned (instance %m)");
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$finish;
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end
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end
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
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if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
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if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
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&& ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
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$display("Overlapping regions:");
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$display("%2d (%2d): %x / %2d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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$display("%2d (%2d): %x / %2d -- %x-%x",
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j/M_REGIONS, j%M_REGIONS,
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M_BASE_ADDR_INT[j],
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M_ADDR_W_INT[j],
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M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
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M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
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);
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$error("Error: address ranges overlap (instance %m)");
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$finish;
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end
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end
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end
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end
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end
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localparam logic [2:0]
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STATE_IDLE = 3'd0,
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STATE_DECODE = 3'd1,
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STATE_WRITE = 3'd2,
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STATE_WRITE_RESP = 3'd3,
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STATE_WRITE_DROP = 3'd4,
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STATE_WAIT_IDLE = 3'd5;
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logic [2:0] state_reg = STATE_IDLE, state_next;
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logic match;
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logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
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logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next;
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logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next;
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logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
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logic [7:0] axi_len_reg = 8'd0, axi_len_next;
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logic [2:0] axi_size_reg = 3'd0, axi_size_next;
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logic [1:0] axi_burst_reg = 2'd0, axi_burst_next;
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logic axi_lock_reg = 1'b0, axi_lock_next;
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logic [3:0] axi_cache_reg = 4'd0, axi_cache_next;
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logic [2:0] axi_prot_reg = 3'b000, axi_prot_next;
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logic [3:0] axi_qos_reg = 4'd0, axi_qos_next;
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logic [3:0] axi_region_reg = 4'd0, axi_region_next;
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logic [AWUSER_W-1:0] axi_awuser_reg = '0, axi_awuser_next;
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logic [1:0] axi_bresp_reg = 2'b00, axi_bresp_next;
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logic [BUSER_W-1:0] axi_buser_reg = '0, axi_buser_next;
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logic [S_COUNT-1:0] s_axi_awready_reg = '0, s_axi_awready_next;
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logic [S_COUNT-1:0] s_axi_wready_reg = '0, s_axi_wready_next;
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logic [S_COUNT-1:0] s_axi_bvalid_reg = '0, s_axi_bvalid_next;
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logic [M_COUNT-1:0] m_axi_awvalid_reg = '0, m_axi_awvalid_next;
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logic [M_COUNT-1:0] m_axi_bready_reg = '0, m_axi_bready_next;
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// internal datapath
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logic [DATA_W-1:0] m_axi_wdata_int;
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logic [STRB_W-1:0] m_axi_wstrb_int;
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logic m_axi_wlast_int;
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logic [WUSER_W-1:0] m_axi_wuser_int;
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logic [M_COUNT-1:0] m_axi_wvalid_int;
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logic m_axi_wready_int_reg = 1'b0;
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wire m_axi_wready_int_early;
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// unpack interface array
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wire [S_ID_W-1:0] s_axi_awid[S_COUNT];
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wire [ADDR_W-1:0] s_axi_addr[S_COUNT];
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wire [7:0] s_axi_awlen[S_COUNT];
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wire [2:0] s_axi_awsize[S_COUNT];
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wire [1:0] s_axi_awburst[S_COUNT];
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wire s_axi_awlock[S_COUNT];
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wire [3:0] s_axi_awcache[S_COUNT];
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wire [2:0] s_axi_awprot[S_COUNT];
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wire [3:0] s_axi_awqos[S_COUNT];
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wire [AWUSER_W-1:0] s_axi_awuser[S_COUNT];
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wire [S_COUNT-1:0] s_axi_awvalid;
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wire [DATA_W-1:0] s_axi_wdata[S_COUNT];
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wire [STRB_W-1:0] s_axi_wstrb[S_COUNT];
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wire s_axi_wlast[S_COUNT];
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wire [WUSER_W-1:0] s_axi_wuser[S_COUNT];
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wire [S_COUNT-1:0] s_axi_wvalid;
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wire [S_COUNT-1:0] s_axi_bready;
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wire [M_COUNT-1:0] m_axi_awready;
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wire [M_ID_W-1:0] m_axi_bid[M_COUNT];
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wire [1:0] m_axi_bresp[M_COUNT];
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wire [BUSER_W-1:0] m_axi_buser[M_COUNT];
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wire [M_COUNT-1:0] m_axi_bvalid;
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for (genvar n = 0; n < S_COUNT; n = n + 1) begin
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assign s_axi_awid[n] = s_axi_wr[n].awid;
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assign s_axi_addr[n] = s_axi_wr[n].awaddr;
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assign s_axi_awlen[n] = s_axi_wr[n].awlen;
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assign s_axi_awsize[n] = s_axi_wr[n].awsize;
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assign s_axi_awburst[n] = s_axi_wr[n].awburst;
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assign s_axi_awlock[n] = s_axi_wr[n].awlock;
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assign s_axi_awcache[n] = s_axi_wr[n].awcache;
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assign s_axi_awprot[n] = s_axi_wr[n].awprot;
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assign s_axi_awqos[n] = s_axi_wr[n].awqos;
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assign s_axi_awuser[n] = s_axi_wr[n].awuser;
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assign s_axi_awvalid[n] = s_axi_wr[n].awvalid;
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assign s_axi_wr[n].awready = s_axi_awready_reg[n];
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assign s_axi_wdata[n] = s_axi_wr[n].wdata;
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assign s_axi_wstrb[n] = s_axi_wr[n].wstrb;
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assign s_axi_wlast[n] = s_axi_wr[n].wlast;
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assign s_axi_wuser[n] = s_axi_wr[n].wuser;
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assign s_axi_wvalid[n] = s_axi_wr[n].wvalid;
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assign s_axi_wr[n].wready = s_axi_wready_reg[n];
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assign s_axi_wr[n].bid = axi_id_reg;
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assign s_axi_wr[n].bresp = axi_bresp_reg;
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assign s_axi_wr[n].buser = BUSER_EN ? axi_buser_reg : '0;
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assign s_axi_wr[n].bvalid = s_axi_bvalid_reg[n];
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assign s_axi_bready[n] = s_axi_wr[n].bready;
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end
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin
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assign m_axi_wr[n].awid = axi_id_reg;
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assign m_axi_wr[n].awaddr = AXI_M_ADDR_W'(axi_addr_reg);
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assign m_axi_wr[n].awlen = axi_len_reg;
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assign m_axi_wr[n].awsize = axi_size_reg;
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assign m_axi_wr[n].awburst = axi_burst_reg;
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assign m_axi_wr[n].awlock = axi_lock_reg;
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assign m_axi_wr[n].awcache = axi_cache_reg;
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assign m_axi_wr[n].awprot = axi_prot_reg;
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assign m_axi_wr[n].awqos = axi_qos_reg;
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assign m_axi_wr[n].awuser = AWUSER_EN ? axi_awuser_reg : '0;
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assign m_axi_wr[n].awvalid = m_axi_awvalid_reg[n];
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assign m_axi_awready[n] = m_axi_wr[n].awready;
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assign m_axi_bid[n] = m_axi_wr[n].bid;
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assign m_axi_bresp[n] = m_axi_wr[n].bresp;
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assign m_axi_buser[n] = m_axi_wr[n].buser;
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assign m_axi_bvalid[n] = m_axi_wr[n].bvalid;
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assign m_axi_wr[n].bready = m_axi_bready_reg[n];
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end
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// slave side mux
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wire [CL_S_COUNT_INT-1:0] s_select;
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wire [S_ID_W-1:0] current_s_axi_awid = s_axi_awid[s_select];
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wire [ADDR_W-1:0] current_s_axi_addr = s_axi_addr[s_select];
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wire [7:0] current_s_axi_awlen = s_axi_awlen[s_select];
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wire [2:0] current_s_axi_awsize = s_axi_awsize[s_select];
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wire [1:0] current_s_axi_awburst = s_axi_awburst[s_select];
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wire current_s_axi_awlock = s_axi_awlock[s_select];
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wire [3:0] current_s_axi_awcache = s_axi_awcache[s_select];
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wire [2:0] current_s_axi_awprot = s_axi_awprot[s_select];
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wire [3:0] current_s_axi_awqos = s_axi_awqos[s_select];
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wire [AWUSER_W-1:0] current_s_axi_awuser = s_axi_awuser[s_select];
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wire current_s_axi_awvalid = s_axi_awvalid[s_select];
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wire [DATA_W-1:0] current_s_axi_wdata = s_axi_wdata[s_select];
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wire [STRB_W-1:0] current_s_axi_wstrb = s_axi_wstrb[s_select];
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wire current_s_axi_wlast = s_axi_wlast[s_select];
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wire [WUSER_W-1:0] current_s_axi_wuser = s_axi_wuser[s_select];
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wire current_s_axi_wvalid = s_axi_wvalid[s_select];
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wire current_s_axi_bready = s_axi_bready[s_select];
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// master side mux
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wire current_m_axi_awready = m_axi_awready[m_select_reg];
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wire current_m_axi_wready = m_axi_wready[m_select_reg];
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wire [M_ID_W-1:0] current_m_axi_bid = m_axi_bid[m_select_reg];
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wire [1:0] current_m_axi_bresp = m_axi_bresp[m_select_reg];
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wire [BUSER_W-1:0] current_m_axi_buser = m_axi_buser[m_select_reg];
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wire current_m_axi_bvalid = m_axi_bvalid[m_select_reg];
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// arbiter instance
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wire [S_COUNT-1:0] req;
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wire [S_COUNT-1:0] ack;
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wire [S_COUNT-1:0] grant;
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wire grant_valid;
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wire [CL_S_COUNT_INT-1:0] grant_index;
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assign s_select = grant_index;
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if (S_COUNT > 1) begin : arb
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taxi_arbiter #(
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.PORTS(S_COUNT),
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.ARB_ROUND_ROBIN(1),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.LSB_HIGH_PRIO(1)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.req(req),
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.ack(ack),
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.grant(grant),
|
|
.grant_valid(grant_valid),
|
|
.grant_index(grant_index)
|
|
);
|
|
|
|
end else begin
|
|
|
|
logic grant_valid_reg = 1'b0;
|
|
|
|
always @(posedge clk) begin
|
|
if (req) begin
|
|
grant_valid_reg <= 1'b1;
|
|
end
|
|
|
|
if (ack || rst) begin
|
|
grant_valid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
assign grant_valid = grant_valid_reg;
|
|
assign grant = '1;
|
|
assign grant_index = '0;
|
|
|
|
end
|
|
|
|
assign req = s_axi_awvalid;
|
|
assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0;
|
|
|
|
always_comb begin
|
|
state_next = STATE_IDLE;
|
|
|
|
match = 1'b0;
|
|
|
|
m_select_next = m_select_reg;
|
|
axi_id_next = axi_id_reg;
|
|
axi_addr_next = axi_addr_reg;
|
|
axi_addr_valid_next = axi_addr_valid_reg;
|
|
axi_len_next = axi_len_reg;
|
|
axi_size_next = axi_size_reg;
|
|
axi_burst_next = axi_burst_reg;
|
|
axi_lock_next = axi_lock_reg;
|
|
axi_cache_next = axi_cache_reg;
|
|
axi_prot_next = axi_prot_reg;
|
|
axi_qos_next = axi_qos_reg;
|
|
axi_region_next = axi_region_reg;
|
|
axi_awuser_next = axi_awuser_reg;
|
|
axi_bresp_next = axi_bresp_reg;
|
|
axi_buser_next = axi_buser_reg;
|
|
|
|
s_axi_awready_next = '0;
|
|
s_axi_wready_next = '0;
|
|
s_axi_bvalid_next = s_axi_bvalid_reg & ~s_axi_bready;
|
|
|
|
m_axi_awvalid_next = m_axi_awvalid_reg & ~m_axi_awready;
|
|
m_axi_bready_next = '0;
|
|
|
|
m_axi_wdata_int = current_s_axi_wdata;
|
|
m_axi_wstrb_int = current_s_axi_wstrb;
|
|
m_axi_wlast_int = current_s_axi_wlast;
|
|
m_axi_wuser_int = current_s_axi_wuser;
|
|
m_axi_wvalid_int = '0;
|
|
|
|
case (state_reg)
|
|
STATE_IDLE: begin
|
|
// idle state; wait for arbitration
|
|
|
|
axi_addr_valid_next = 1'b1;
|
|
axi_id_next = current_s_axi_awid;
|
|
axi_addr_next = current_s_axi_addr;
|
|
axi_len_next = current_s_axi_awlen;
|
|
axi_size_next = current_s_axi_awsize;
|
|
axi_burst_next = current_s_axi_awburst;
|
|
axi_lock_next = current_s_axi_awlock;
|
|
axi_cache_next = current_s_axi_awcache;
|
|
axi_prot_next = current_s_axi_awprot;
|
|
axi_qos_next = current_s_axi_awqos;
|
|
axi_awuser_next = current_s_axi_awuser;
|
|
|
|
if (grant_valid) begin
|
|
s_axi_awready_next[s_select] = 1'b1;
|
|
state_next = STATE_DECODE;
|
|
end else begin
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end
|
|
STATE_DECODE: begin
|
|
// decode state; determine master interface
|
|
|
|
match = 1'b0;
|
|
for (integer i = 0; i < M_COUNT; i = i + 1) begin
|
|
for (integer j = 0; j < M_REGIONS; j = j + 1) begin
|
|
if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
|
|
m_select_next = CL_M_COUNT_INT'(i);
|
|
match = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
axi_bresp_next = 2'b11;
|
|
|
|
if (match) begin
|
|
s_axi_wready_next[s_select] = m_axi_wready_int_early;
|
|
state_next = STATE_WRITE;
|
|
end else begin
|
|
// no match; return decode error
|
|
s_axi_wready_next[s_select] = 1'b1;
|
|
state_next = STATE_WRITE_DROP;
|
|
end
|
|
end
|
|
STATE_WRITE: begin
|
|
// write state; store and forward write data
|
|
s_axi_wready_next[s_select] = m_axi_wready_int_early;
|
|
|
|
if (axi_addr_valid_reg) begin
|
|
m_axi_awvalid_next[m_select_reg] = 1'b1;
|
|
end
|
|
axi_addr_valid_next = 1'b0;
|
|
|
|
m_axi_wdata_int = current_s_axi_wdata;
|
|
m_axi_wstrb_int = current_s_axi_wstrb;
|
|
m_axi_wlast_int = current_s_axi_wlast;
|
|
m_axi_wuser_int = current_s_axi_wuser;
|
|
|
|
if (s_axi_wready_reg != 0 && current_s_axi_wvalid) begin
|
|
m_axi_wvalid_int[m_select_reg] = 1'b1;
|
|
|
|
if (current_s_axi_wlast) begin
|
|
s_axi_wready_next[s_select] = 1'b0;
|
|
m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
|
|
state_next = STATE_WRITE_RESP;
|
|
end else begin
|
|
state_next = STATE_WRITE;
|
|
end
|
|
end else begin
|
|
state_next = STATE_WRITE;
|
|
end
|
|
end
|
|
STATE_WRITE_RESP: begin
|
|
// write response state; store and forward write response
|
|
m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
|
|
|
|
if (m_axi_bready_reg != 0 && current_m_axi_bvalid) begin
|
|
m_axi_bready_next[m_select_reg] = 1'b0;
|
|
axi_bresp_next = current_m_axi_bresp;
|
|
s_axi_bvalid_next[s_select] = 1'b1;
|
|
state_next = STATE_WAIT_IDLE;
|
|
end else begin
|
|
state_next = STATE_WRITE_RESP;
|
|
end
|
|
end
|
|
STATE_WRITE_DROP: begin
|
|
// write drop state; drop write data
|
|
s_axi_wready_next[s_select] = 1'b1;
|
|
|
|
axi_addr_valid_next = 1'b0;
|
|
|
|
if (s_axi_wready_reg != 0 && current_s_axi_wvalid && current_s_axi_wlast) begin
|
|
s_axi_wready_next[s_select] = 1'b0;
|
|
s_axi_bvalid_next[s_select] = 1'b1;
|
|
state_next = STATE_WAIT_IDLE;
|
|
end else begin
|
|
state_next = STATE_WRITE_DROP;
|
|
end
|
|
end
|
|
STATE_WAIT_IDLE: begin
|
|
// wait for idle state; wait untl grant valid is deasserted
|
|
|
|
if (grant_valid == 0 || ack != 0) begin
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
state_next = STATE_WAIT_IDLE;
|
|
end
|
|
end
|
|
default: begin
|
|
// invalid state
|
|
state_next = STATE_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
s_axi_awready_reg <= s_axi_awready_next;
|
|
s_axi_wready_reg <= s_axi_wready_next;
|
|
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
|
|
|
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
|
m_axi_bready_reg <= m_axi_bready_next;
|
|
|
|
m_select_reg <= m_select_next;
|
|
axi_id_reg <= axi_id_next;
|
|
axi_addr_reg <= axi_addr_next;
|
|
axi_addr_valid_reg <= axi_addr_valid_next;
|
|
axi_len_reg <= axi_len_next;
|
|
axi_size_reg <= axi_size_next;
|
|
axi_burst_reg <= axi_burst_next;
|
|
axi_lock_reg <= axi_lock_next;
|
|
axi_cache_reg <= axi_cache_next;
|
|
axi_prot_reg <= axi_prot_next;
|
|
axi_qos_reg <= axi_qos_next;
|
|
axi_region_reg <= axi_region_next;
|
|
axi_awuser_reg <= axi_awuser_next;
|
|
axi_bresp_reg <= axi_bresp_next;
|
|
axi_buser_reg <= axi_buser_next;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
s_axi_awready_reg <= '0;
|
|
s_axi_wready_reg <= '0;
|
|
s_axi_bvalid_reg <= '0;
|
|
|
|
m_axi_awvalid_reg <= '0;
|
|
m_axi_bready_reg <= '0;
|
|
end
|
|
end
|
|
|
|
// output datapath logic (W channel)
|
|
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
|
|
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
|
|
logic m_axi_wlast_reg = 1'b0;
|
|
logic [WUSER_W-1:0] m_axi_wuser_reg = 1'b0;
|
|
logic [M_COUNT-1:0] m_axi_wvalid_reg = '0, m_axi_wvalid_next;
|
|
|
|
logic [DATA_W-1:0] temp_m_axi_wdata_reg = '0;
|
|
logic [STRB_W-1:0] temp_m_axi_wstrb_reg = '0;
|
|
logic temp_m_axi_wlast_reg = 1'b0;
|
|
logic [WUSER_W-1:0] temp_m_axi_wuser_reg = 1'b0;
|
|
logic [M_COUNT-1:0] temp_m_axi_wvalid_reg = '0, temp_m_axi_wvalid_next;
|
|
|
|
// datapath control
|
|
logic store_axi_w_int_to_output;
|
|
logic store_axi_w_int_to_temp;
|
|
logic store_axi_w_temp_to_output;
|
|
|
|
wire [M_COUNT-1:0] m_axi_wready;
|
|
|
|
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
|
|
assign m_axi_wr[n].wdata = m_axi_wdata_reg;
|
|
assign m_axi_wr[n].wstrb = m_axi_wstrb_reg;
|
|
assign m_axi_wr[n].wlast = m_axi_wlast_reg;
|
|
assign m_axi_wr[n].wuser = WUSER_EN ? m_axi_wuser_reg : '0;
|
|
assign m_axi_wr[n].wvalid = m_axi_wvalid_reg[n];
|
|
assign m_axi_wready[n] = m_axi_wr[n].wready;
|
|
end
|
|
|
|
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
|
assign m_axi_wready_int_early = (m_axi_wready & m_axi_wvalid_reg) != 0 || (temp_m_axi_wvalid_reg == 0 && (m_axi_wvalid_reg == 0 || m_axi_wvalid_int == 0));
|
|
|
|
always_comb begin
|
|
// transfer sink ready state to source
|
|
m_axi_wvalid_next = m_axi_wvalid_reg;
|
|
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
|
|
|
store_axi_w_int_to_output = 1'b0;
|
|
store_axi_w_int_to_temp = 1'b0;
|
|
store_axi_w_temp_to_output = 1'b0;
|
|
|
|
if (m_axi_wready_int_reg) begin
|
|
// input is ready
|
|
if ((m_axi_wready & m_axi_wvalid_reg) != 0 || m_axi_wvalid_reg == 0) begin
|
|
// output is ready or currently not valid, transfer data to output
|
|
m_axi_wvalid_next = m_axi_wvalid_int;
|
|
store_axi_w_int_to_output = 1'b1;
|
|
end else begin
|
|
// output is not ready, store input in temp
|
|
temp_m_axi_wvalid_next = m_axi_wvalid_int;
|
|
store_axi_w_int_to_temp = 1'b1;
|
|
end
|
|
end else if ((m_axi_wready & m_axi_wvalid_reg) != 0) begin
|
|
// input is not ready, but output is ready
|
|
m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
|
temp_m_axi_wvalid_next = '0;
|
|
store_axi_w_temp_to_output = 1'b1;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
|
m_axi_wready_int_reg <= m_axi_wready_int_early;
|
|
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
|
|
|
|
// datapath
|
|
if (store_axi_w_int_to_output) begin
|
|
m_axi_wdata_reg <= m_axi_wdata_int;
|
|
m_axi_wstrb_reg <= m_axi_wstrb_int;
|
|
m_axi_wlast_reg <= m_axi_wlast_int;
|
|
m_axi_wuser_reg <= m_axi_wuser_int;
|
|
end else if (store_axi_w_temp_to_output) begin
|
|
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
|
|
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
|
|
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
|
|
m_axi_wuser_reg <= temp_m_axi_wuser_reg;
|
|
end
|
|
|
|
if (store_axi_w_int_to_temp) begin
|
|
temp_m_axi_wdata_reg <= m_axi_wdata_int;
|
|
temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
|
|
temp_m_axi_wlast_reg <= m_axi_wlast_int;
|
|
temp_m_axi_wuser_reg <= m_axi_wuser_int;
|
|
end
|
|
|
|
if (rst) begin
|
|
m_axi_wvalid_reg <= '0;
|
|
m_axi_wready_int_reg <= 1'b0;
|
|
temp_m_axi_wvalid_reg <= '0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|