Add write dma

sim/alibaba_pcie.py

@@ -117,5 +117,16 @@ async def test_sanity(dut):
     await dev_bar0.write_dword(0xc, len(message))
     await dev_bar0.write_dword(0x10, 0x00000001)
 
+    await Timer(100, "ns")
 
-    await Timer(10, "us")
+    await dev_bar0.write_dword(0x20, 0x00000100)
+    await dev_bar0.write_dword(0x24, 0x00000000)
+    await dev_bar0.write_dword(0x28, 0x00000000)
+    await dev_bar0.write_dword(0x2c, len(message))
+    await dev_bar0.write_dword(0x30, 0x00000001)
+
+    await Timer(10, "us")
+
+    read_msg = await mem.read(0x100, len(message))
+
+    tb.log.info(read_msg)

src/alibaba_pcie_top.sv

@@ -54,7 +54,7 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
 taxi_axil_if m_axil_rd();
 taxi_axil_if m_axil_wr();
 
-taxi_apb_if #(.ADDR_W(5)) m_apb();
+taxi_apb_if #(.ADDR_W(6)) m_apb();
 
 `ifndef SIM
 IBUFDS_GTE4 m_ibufds (

src/pcie_dma_wrapper.sv

@@ -54,14 +54,19 @@ taxi_dma_psdpram #(
 );
 
 logic [7:0] read_tag;
+logic [7:0] write_tag;
 
 always_ff @(posedge clk) begin
     if (rst) begin
         read_tag <= '0;
+        write_tag <= '0;
     end else begin
         if (rd_desc.req_valid && rd_desc.req_ready) begin
             read_tag <= read_tag + 1;
         end
+        if (wr_desc.req_valid && wr_desc.req_ready) begin
+            write_tag <= write_tag + 1;
+        end
     end
 end
 
@@ -78,12 +83,24 @@ always_comb begin
     rd_desc.req_id = '0;
     rd_desc.req_dest = '0;
     rd_desc.req_user = '0;
-
     rd_desc.req_valid = hwif_out.dma_rd.trigger.trigger.value;
-
     hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
-
     hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
+
+    wr_desc.req_src_addr = hwif_out.dma_wr.src_addr.addr.value;
+    wr_desc.req_src_sel = '0;
+    wr_desc.req_dst_addr = {hwif_out.dma_wr.dst_addr_high.addr.value, hwif_out.dma_wr.dst_addr_low.addr.value};
+    wr_desc.req_dst_sel = '0;
+    wr_desc.req_imm = '0;
+    wr_desc.req_imm_en = '0;
+    wr_desc.req_len = hwif_out.dma_wr.length.len.value;
+    wr_desc.req_tag = write_tag;
+    wr_desc.req_id = '0;
+    wr_desc.req_dest = '0;
+    wr_desc.req_user = '0;
+    wr_desc.req_valid = hwif_out.dma_wr.trigger.trigger.value;
+    hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
+    hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
 end
 
 

src/regs/pcie_dma_regs.rdl

@@ -85,4 +85,88 @@ addrmap pcie_dma_regs {
             
         } done @ 0x14;
     } dma_rd @ 0x0;
+
+    regfile {
+        reg {
+            name = "DMA Read Dest Address Low";
+            desc = "Address which will be written to over PCIe (System Address)";
+
+            field {
+                name = "addr";
+                desc = "";
+                hw   = r;
+                sw   = rw;
+            } addr[31:0] = 0x0;
+            
+        } dst_addr_low @ 0x0;
+
+        reg {
+            name = "DMA Read Dest Address High";
+            desc = "Address which will be written to over PCIe (System Address)";
+
+            field {
+                name = "addr";
+                desc = "";
+                hw   = r;
+                sw   = rw;
+            } addr[31:0] = 0x0;
+            
+        } dst_addr_high @ 0x4;
+
+        reg {
+            name = "DMA Read Source Address";
+            desc = "Address where data will be read from on chip (Local Address)";
+
+            field {
+                name = "addr";
+                desc = "";
+                hw   = r;
+                sw   = rw;
+            } addr[15:0] = 0x0;
+            
+        } src_addr @ 0x8;
+
+        reg {
+            name = "Length";
+            desc = "";
+
+            field {
+                name = "Length";
+                desc = "";
+                hw   = r;
+                sw   = rw;
+            } len[15:0] = 0x0;
+            
+        } length @ 0xc;
+
+        reg {
+            name = "Trigger";
+            desc = "Trigger DMA";
+
+            field {
+                name = "Trigger";
+                desc = "";
+                hwclr;
+
+                hw   = r;
+                sw   = w;
+            } trigger[0:0] = 0x0;
+            
+        } trigger @ 0x10;
+
+        reg {
+            name = "Done";
+            desc = "DMA is done";
+
+            field {
+                name = "Done";
+                desc = "";
+                hwset;
+                rclr;
+                hw   = r;
+                sw   = r;
+            } done[0:0] = 0x0;
+            
+        } done @ 0x14;
+    } dma_wr @ 0x20;
 };

src/regs/pcie_dma_regs.sv

@@ -9,7 +9,7 @@ module pcie_dma_regs (
         input wire s_apb_penable,
         input wire s_apb_pwrite,
         input wire [2:0] s_apb_pprot,
-        input wire [4:0] s_apb_paddr,
+        input wire [5:0] s_apb_paddr,
         input wire [31:0] s_apb_pwdata,
         input wire [3:0] s_apb_pstrb,
         output logic s_apb_pready,
@@ -25,7 +25,7 @@ module pcie_dma_regs (
     //--------------------------------------------------------------------------
     logic cpuif_req;
     logic cpuif_req_is_wr;
-    logic [4:0] cpuif_addr;
+    logic [5:0] cpuif_addr;
     logic [31:0] cpuif_wr_data;
     logic [31:0] cpuif_wr_biten;
     logic cpuif_req_stall_wr;
@@ -54,7 +54,7 @@ module pcie_dma_regs (
                     is_active <= '1;
                     cpuif_req <= '1;
                     cpuif_req_is_wr <= s_apb_pwrite;
-                    cpuif_addr <= {s_apb_paddr[4:2], 2'b0};
+                    cpuif_addr <= {s_apb_paddr[5:2], 2'b0};
                     cpuif_wr_data <= s_apb_pwdata;
                     for(int i=0; i<4; i++) begin
                         cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
@@ -95,6 +95,14 @@ module pcie_dma_regs (
             logic trigger;
             logic done;
         } dma_rd;
+        struct {
+            logic dst_addr_low;
+            logic dst_addr_high;
+            logic src_addr;
+            logic length;
+            logic trigger;
+            logic done;
+        } dma_wr;
     } decoded_reg_strb_t;
     decoded_reg_strb_t decoded_reg_strb;
     logic decoded_err;
@@ -108,12 +116,18 @@ module pcie_dma_regs (
         automatic logic is_invalid_rw;
         is_valid_addr = '1; // No error checking on valid address access
         is_invalid_rw = '0;
-        decoded_reg_strb.dma_rd.src_addr_low = cpuif_req_masked & (cpuif_addr == 5'h0);
-        decoded_reg_strb.dma_rd.src_addr_high = cpuif_req_masked & (cpuif_addr == 5'h4);
-        decoded_reg_strb.dma_rd.dst_addr = cpuif_req_masked & (cpuif_addr == 5'h8);
-        decoded_reg_strb.dma_rd.length = cpuif_req_masked & (cpuif_addr == 5'hc);
-        decoded_reg_strb.dma_rd.trigger = cpuif_req_masked & (cpuif_addr == 5'h10) & cpuif_req_is_wr;
-        decoded_reg_strb.dma_rd.done = cpuif_req_masked & (cpuif_addr == 5'h14) & !cpuif_req_is_wr;
+        decoded_reg_strb.dma_rd.src_addr_low = cpuif_req_masked & (cpuif_addr == 6'h0);
+        decoded_reg_strb.dma_rd.src_addr_high = cpuif_req_masked & (cpuif_addr == 6'h4);
+        decoded_reg_strb.dma_rd.dst_addr = cpuif_req_masked & (cpuif_addr == 6'h8);
+        decoded_reg_strb.dma_rd.length = cpuif_req_masked & (cpuif_addr == 6'hc);
+        decoded_reg_strb.dma_rd.trigger = cpuif_req_masked & (cpuif_addr == 6'h10) & cpuif_req_is_wr;
+        decoded_reg_strb.dma_rd.done = cpuif_req_masked & (cpuif_addr == 6'h14) & !cpuif_req_is_wr;
+        decoded_reg_strb.dma_wr.dst_addr_low = cpuif_req_masked & (cpuif_addr == 6'h20);
+        decoded_reg_strb.dma_wr.dst_addr_high = cpuif_req_masked & (cpuif_addr == 6'h24);
+        decoded_reg_strb.dma_wr.src_addr = cpuif_req_masked & (cpuif_addr == 6'h28);
+        decoded_reg_strb.dma_wr.length = cpuif_req_masked & (cpuif_addr == 6'h2c);
+        decoded_reg_strb.dma_wr.trigger = cpuif_req_masked & (cpuif_addr == 6'h30) & cpuif_req_is_wr;
+        decoded_reg_strb.dma_wr.done = cpuif_req_masked & (cpuif_addr == 6'h34) & !cpuif_req_is_wr;
         decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
     end
 
@@ -165,6 +179,44 @@ module pcie_dma_regs (
                 } done;
             } done;
         } dma_rd;
+        struct {
+            struct {
+                struct {
+                    logic [31:0] next;
+                    logic load_next;
+                } addr;
+            } dst_addr_low;
+            struct {
+                struct {
+                    logic [31:0] next;
+                    logic load_next;
+                } addr;
+            } dst_addr_high;
+            struct {
+                struct {
+                    logic [15:0] next;
+                    logic load_next;
+                } addr;
+            } src_addr;
+            struct {
+                struct {
+                    logic [15:0] next;
+                    logic load_next;
+                } len;
+            } length;
+            struct {
+                struct {
+                    logic next;
+                    logic load_next;
+                } trigger;
+            } trigger;
+            struct {
+                struct {
+                    logic next;
+                    logic load_next;
+                } done;
+            } done;
+        } dma_wr;
     } field_combo_t;
     field_combo_t field_combo;
 
@@ -201,6 +253,38 @@ module pcie_dma_regs (
                 } done;
             } done;
         } dma_rd;
+        struct {
+            struct {
+                struct {
+                    logic [31:0] value;
+                } addr;
+            } dst_addr_low;
+            struct {
+                struct {
+                    logic [31:0] value;
+                } addr;
+            } dst_addr_high;
+            struct {
+                struct {
+                    logic [15:0] value;
+                } addr;
+            } src_addr;
+            struct {
+                struct {
+                    logic [15:0] value;
+                } len;
+            } length;
+            struct {
+                struct {
+                    logic value;
+                } trigger;
+            } trigger;
+            struct {
+                struct {
+                    logic value;
+                } done;
+            } done;
+        } dma_wr;
     } field_storage_t;
     field_storage_t field_storage;
 
@@ -348,6 +432,150 @@ module pcie_dma_regs (
         end
     end
     assign hwif_out.dma_rd.done.done.value = field_storage.dma_rd.done.done.value;
+    // Field: pcie_dma_regs.dma_wr.dst_addr_low.addr
+    always_comb begin
+        automatic logic [31:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.dst_addr_low.addr.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.dst_addr_low && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.dma_wr.dst_addr_low.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.dst_addr_low.addr.next = next_c;
+        field_combo.dma_wr.dst_addr_low.addr.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.dst_addr_low.addr.value <= 32'h0;
+        end else begin
+            if(field_combo.dma_wr.dst_addr_low.addr.load_next) begin
+                field_storage.dma_wr.dst_addr_low.addr.value <= field_combo.dma_wr.dst_addr_low.addr.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.dst_addr_low.addr.value = field_storage.dma_wr.dst_addr_low.addr.value;
+    // Field: pcie_dma_regs.dma_wr.dst_addr_high.addr
+    always_comb begin
+        automatic logic [31:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.dst_addr_high.addr.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.dst_addr_high && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.dma_wr.dst_addr_high.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.dst_addr_high.addr.next = next_c;
+        field_combo.dma_wr.dst_addr_high.addr.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.dst_addr_high.addr.value <= 32'h0;
+        end else begin
+            if(field_combo.dma_wr.dst_addr_high.addr.load_next) begin
+                field_storage.dma_wr.dst_addr_high.addr.value <= field_combo.dma_wr.dst_addr_high.addr.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.dst_addr_high.addr.value = field_storage.dma_wr.dst_addr_high.addr.value;
+    // Field: pcie_dma_regs.dma_wr.src_addr.addr
+    always_comb begin
+        automatic logic [15:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.src_addr.addr.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.src_addr && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.dma_wr.src_addr.addr.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.src_addr.addr.next = next_c;
+        field_combo.dma_wr.src_addr.addr.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.src_addr.addr.value <= 16'h0;
+        end else begin
+            if(field_combo.dma_wr.src_addr.addr.load_next) begin
+                field_storage.dma_wr.src_addr.addr.value <= field_combo.dma_wr.src_addr.addr.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.src_addr.addr.value = field_storage.dma_wr.src_addr.addr.value;
+    // Field: pcie_dma_regs.dma_wr.length.len
+    always_comb begin
+        automatic logic [15:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.length.len.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.length && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.dma_wr.length.len.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.length.len.next = next_c;
+        field_combo.dma_wr.length.len.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.length.len.value <= 16'h0;
+        end else begin
+            if(field_combo.dma_wr.length.len.load_next) begin
+                field_storage.dma_wr.length.len.value <= field_combo.dma_wr.length.len.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.length.len.value = field_storage.dma_wr.length.len.value;
+    // Field: pcie_dma_regs.dma_wr.trigger.trigger
+    always_comb begin
+        automatic logic [0:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.trigger.trigger.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.trigger && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.dma_wr.trigger.trigger.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end else if(hwif_in.dma_wr.trigger.trigger.hwclr) begin // HW Clear
+            next_c = '0;
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.trigger.trigger.next = next_c;
+        field_combo.dma_wr.trigger.trigger.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.trigger.trigger.value <= 1'h0;
+        end else begin
+            if(field_combo.dma_wr.trigger.trigger.load_next) begin
+                field_storage.dma_wr.trigger.trigger.value <= field_combo.dma_wr.trigger.trigger.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.trigger.trigger.value = field_storage.dma_wr.trigger.trigger.value;
+    // Field: pcie_dma_regs.dma_wr.done.done
+    always_comb begin
+        automatic logic [0:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.dma_wr.done.done.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.dma_wr.done && !decoded_req_is_wr) begin // SW clear on read
+            next_c = '0;
+            load_next_c = '1;
+        end else if(hwif_in.dma_wr.done.done.hwset) begin // HW Set
+            next_c = '1;
+            load_next_c = '1;
+        end
+        field_combo.dma_wr.done.done.next = next_c;
+        field_combo.dma_wr.done.done.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.dma_wr.done.done.value <= 1'h0;
+        end else begin
+            if(field_combo.dma_wr.done.done.load_next) begin
+                field_storage.dma_wr.done.done.value <= field_combo.dma_wr.done.done.next;
+            end
+        end
+    end
+    assign hwif_out.dma_wr.done.done.value = field_storage.dma_wr.done.done.value;
 
     //--------------------------------------------------------------------------
     // Write response
@@ -365,7 +593,7 @@ module pcie_dma_regs (
     logic [31:0] readback_data;
 
     // Assign readback values to a flattened array
-    logic [31:0] readback_array[5];
+    logic [31:0] readback_array[10];
     assign readback_array[0][31:0] = (decoded_reg_strb.dma_rd.src_addr_low && !decoded_req_is_wr) ? field_storage.dma_rd.src_addr_low.addr.value : '0;
     assign readback_array[1][31:0] = (decoded_reg_strb.dma_rd.src_addr_high && !decoded_req_is_wr) ? field_storage.dma_rd.src_addr_high.addr.value : '0;
     assign readback_array[2][15:0] = (decoded_reg_strb.dma_rd.dst_addr && !decoded_req_is_wr) ? field_storage.dma_rd.dst_addr.addr.value : '0;
@@ -374,6 +602,14 @@ module pcie_dma_regs (
     assign readback_array[3][31:16] = '0;
     assign readback_array[4][0:0] = (decoded_reg_strb.dma_rd.done && !decoded_req_is_wr) ? field_storage.dma_rd.done.done.value : '0;
     assign readback_array[4][31:1] = '0;
+    assign readback_array[5][31:0] = (decoded_reg_strb.dma_wr.dst_addr_low && !decoded_req_is_wr) ? field_storage.dma_wr.dst_addr_low.addr.value : '0;
+    assign readback_array[6][31:0] = (decoded_reg_strb.dma_wr.dst_addr_high && !decoded_req_is_wr) ? field_storage.dma_wr.dst_addr_high.addr.value : '0;
+    assign readback_array[7][15:0] = (decoded_reg_strb.dma_wr.src_addr && !decoded_req_is_wr) ? field_storage.dma_wr.src_addr.addr.value : '0;
+    assign readback_array[7][31:16] = '0;
+    assign readback_array[8][15:0] = (decoded_reg_strb.dma_wr.length && !decoded_req_is_wr) ? field_storage.dma_wr.length.len.value : '0;
+    assign readback_array[8][31:16] = '0;
+    assign readback_array[9][0:0] = (decoded_reg_strb.dma_wr.done && !decoded_req_is_wr) ? field_storage.dma_wr.done.done.value : '0;
+    assign readback_array[9][31:1] = '0;
 
     // Reduce the array
     always_comb begin
@@ -381,7 +617,7 @@ module pcie_dma_regs (
         readback_done = decoded_req & ~decoded_req_is_wr;
         readback_err = '0;
         readback_data_var = '0;
-        for(int i=0; i<5; i++) readback_data_var |= readback_array[i];
+        for(int i=0; i<10; i++) readback_data_var |= readback_array[i];
         readback_data = readback_data_var;
     end
 

src/regs/pcie_dma_regs_pkg.sv

@@ -4,8 +4,8 @@
 package pcie_dma_regs_pkg;
 
     localparam PCIE_DMA_REGS_DATA_WIDTH = 32;
-    localparam PCIE_DMA_REGS_MIN_ADDR_WIDTH = 5;
-    localparam PCIE_DMA_REGS_SIZE = 'h18;
+    localparam PCIE_DMA_REGS_MIN_ADDR_WIDTH = 6;
+    localparam PCIE_DMA_REGS_SIZE = 'h38;
 
     typedef struct {
         logic hwclr;
@@ -28,8 +28,30 @@ package pcie_dma_regs_pkg;
         pcie_dma_regs__dma_rd__done__in_t done;
     } pcie_dma_regs__dma_rd__in_t;
 
+    typedef struct {
+        logic hwclr;
+    } pcie_dma_regs__dma_wr__trigger__trigger__in_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__trigger__trigger__in_t trigger;
+    } pcie_dma_regs__dma_wr__trigger__in_t;
+
+    typedef struct {
+        logic hwset;
+    } pcie_dma_regs__dma_wr__done__done__in_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__done__done__in_t done;
+    } pcie_dma_regs__dma_wr__done__in_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__trigger__in_t trigger;
+        pcie_dma_regs__dma_wr__done__in_t done;
+    } pcie_dma_regs__dma_wr__in_t;
+
     typedef struct {
         pcie_dma_regs__dma_rd__in_t dma_rd;
+        pcie_dma_regs__dma_wr__in_t dma_wr;
     } pcie_dma_regs__in_t;
 
     typedef struct {
@@ -89,7 +111,65 @@ package pcie_dma_regs_pkg;
         pcie_dma_regs__dma_rd__done__out_t done;
     } pcie_dma_regs__dma_rd__out_t;
 
+    typedef struct {
+        logic [31:0] value;
+    } pcie_dma_regs__dma_wr__dst_addr_low__addr__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__dst_addr_low__addr__out_t addr;
+    } pcie_dma_regs__dma_wr__dst_addr_low__out_t;
+
+    typedef struct {
+        logic [31:0] value;
+    } pcie_dma_regs__dma_wr__dst_addr_high__addr__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__dst_addr_high__addr__out_t addr;
+    } pcie_dma_regs__dma_wr__dst_addr_high__out_t;
+
+    typedef struct {
+        logic [15:0] value;
+    } pcie_dma_regs__dma_wr__src_addr__addr__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__src_addr__addr__out_t addr;
+    } pcie_dma_regs__dma_wr__src_addr__out_t;
+
+    typedef struct {
+        logic [15:0] value;
+    } pcie_dma_regs__dma_wr__length__len__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__length__len__out_t len;
+    } pcie_dma_regs__dma_wr__length__out_t;
+
+    typedef struct {
+        logic value;
+    } pcie_dma_regs__dma_wr__trigger__trigger__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__trigger__trigger__out_t trigger;
+    } pcie_dma_regs__dma_wr__trigger__out_t;
+
+    typedef struct {
+        logic value;
+    } pcie_dma_regs__dma_wr__done__done__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__done__done__out_t done;
+    } pcie_dma_regs__dma_wr__done__out_t;
+
+    typedef struct {
+        pcie_dma_regs__dma_wr__dst_addr_low__out_t dst_addr_low;
+        pcie_dma_regs__dma_wr__dst_addr_high__out_t dst_addr_high;
+        pcie_dma_regs__dma_wr__src_addr__out_t src_addr;
+        pcie_dma_regs__dma_wr__length__out_t length;
+        pcie_dma_regs__dma_wr__trigger__out_t trigger;
+        pcie_dma_regs__dma_wr__done__out_t done;
+    } pcie_dma_regs__dma_wr__out_t;
+
     typedef struct {
         pcie_dma_regs__dma_rd__out_t dma_rd;
+        pcie_dma_regs__dma_wr__out_t dma_wr;
     } pcie_dma_regs__out_t;
 endpackage