37 lines
929 B
Systemverilog
37 lines
929 B
Systemverilog
module pcie_dma_wrapper (
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input logic clk,
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input logic rst,
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taxi_axis_if.src m_axis_rq,
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taxi_axis_if.snk s_axis_rc,
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taxi_apb_if.slv s_apb
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);
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logic [5:0] seq_num_0;
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logic seq_num_valid_0;
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logic [5:0] seq_num_1;
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logic seq_num_valid_1;
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taxi_dma_if_pcie_us #(
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) u_taxi_dma_if_pcie_us (
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.clk (clk),
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.rst (rst),
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.m_axis_rq (m_axis_rq),
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.m_axis_rc (m_axis_rc),
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.s_axis_rq_seq_num_0 (seq_num_0),
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.s_axis_rq_seq_num_valid_0 (seq_num_valid_0),
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.s_axis_rq_seq_num_1 (seq_num_1),
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.s_axis_rq_seq_num_valid_1 (seq_num_valid_1),
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.pcie_tx_fc_nph_av ('0),
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.pcie_tx_fc_ph_av ('0),
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.pcie_tx_fc_pd_av ('0),
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);
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endmodule |