178 lines
4.8 KiB
Systemverilog
178 lines
4.8 KiB
Systemverilog
module pcie_top(
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input wire [7:0] pci_exp_rxp,
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input wire [7:0] pci_exp_rxn,
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output wire [7:0] pci_exp_txp,
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output wire [7:0] pci_exp_txn,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_reset_n,
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output wire user_lnk_up,
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output wire phy_rdy_out,
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taxi_dma_ram_if.wr_slv dma_ram_eth_wr_if,
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taxi_dma_ram_if.rd_slv dma_ram_eth_rd_if,
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taxi_axil_if.rd_mst m_axil_rd,
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taxi_axil_if.wr_mst m_axil_wr,
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taxi_apb_if.slv s_apb
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);
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logic clk_pcie_gt;
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logic clk_pcie;
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logic rst_pcie;
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logic clk_250;
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logic rst_250;
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logic user_lnk_up;
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logic phy_rdy_out;
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taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
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taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
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taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
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taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
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taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb();
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`ifndef SIM
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IBUFDS_GTE4 m_ibufds (
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.CEB('0),
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.I(pcie_mgt_refclk_p),
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.IB(pcie_mgt_refclk_n),
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.O(clk_pcie_gt),
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.ODIV2(clk_pcie)
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);
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`endif
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pcie_top_regs u_pcie_top_regs (
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.s_apb (s_apb),
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.m_apb_pcie_dma_regs(pcie_dma_apb)
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)
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taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
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.clk (clk_250),
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.rst (rst_250),
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.s_axis_cq (m_axis_cq),
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.m_axis_cc (s_axis_cc),
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.m_axil_wr (m_axil_wr),
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.m_axil_rd (m_axil_rd),
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.completer_id ('0),
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.completer_id_en ('0),
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.stat_err_cor (),
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.stat_err_uncor ()
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);
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taxi_dma_psdpram #(
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.SIZE(16384)
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) u_taxi_dma_tx_psdpram (
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.clk (clk_250),
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.rst (rst_250),
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.dma_ram_wr (dma_ram_pcie_wr_if),
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.dma_ram_rd (dma_ram_eth_rd_if)
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);
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taxi_dma_psdpram #(
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.SIZE(16384)
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) u_taxi_dma_rx_psdpram(
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.clk (clk_250),
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.rst (rst_250),
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.dma_ram_wr (dma_ram_eth_wr_if),
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.dma_ram_rd (dma_ram_pcie_rd_if)
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);
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pcie_dma_wrapper u_pcie_dma_wrapper (
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.clk (clk_250),
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.rst (rst_250),
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.m_axis_rq (s_axis_rq),
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.s_axis_rc (m_axis_rc),
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.wr_dma_mst (dma_ram_pcie_wr_if),
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.rd_dma_mst (dma_ram_pcie_rd_if),
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.s_apb (pcie_dma_apb)
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);
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`ifndef SIM
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pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
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.pci_exp_txn(pci_exp_txn),
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.pci_exp_txp(pci_exp_txp),
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.pci_exp_rxn(pci_exp_rxn),
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.pci_exp_rxp(pci_exp_rxp),
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.user_clk(clk_250),
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.user_reset(rst_250),
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.user_lnk_up(user_lnk_up),
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.s_axis_rq_tdata(s_axis_rq.tdata),
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.s_axis_rq_tkeep(s_axis_rq.tkeep),
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.s_axis_rq_tlast(s_axis_rq.tlast),
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.s_axis_rq_tready(s_axis_rq.tready),
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.s_axis_rq_tuser(s_axis_rq.tuser),
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.s_axis_rq_tvalid(s_axis_rq.tvalid),
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.m_axis_rc_tdata(m_axis_rc.tdata),
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.m_axis_rc_tkeep(m_axis_rc.tkeep),
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.m_axis_rc_tlast(m_axis_rc.tlast),
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.m_axis_rc_tready(m_axis_rc.tready),
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.m_axis_rc_tuser(m_axis_rc.tuser),
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.m_axis_rc_tvalid(m_axis_rc.tvalid),
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.m_axis_cq_tdata(m_axis_cq.tdata),
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.m_axis_cq_tkeep(m_axis_cq.tkeep),
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.m_axis_cq_tlast(m_axis_cq.tlast),
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.m_axis_cq_tready(m_axis_cq.tready),
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.m_axis_cq_tuser(m_axis_cq.tuser),
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.m_axis_cq_tvalid(m_axis_cq.tvalid),
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.s_axis_cc_tdata(s_axis_cc.tdata),
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.s_axis_cc_tkeep(s_axis_cc.tkeep),
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.s_axis_cc_tlast(s_axis_cc.tlast),
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.s_axis_cc_tready(s_axis_cc.tready),
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.s_axis_cc_tuser(s_axis_cc.tuser),
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.s_axis_cc_tvalid(s_axis_cc.tvalid),
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.cfg_interrupt_int('0),
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.cfg_interrupt_pending(),
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.cfg_interrupt_sent('0),
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.cfg_interrupt_msi_enable(),
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.cfg_interrupt_msi_mmenable(),
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.cfg_interrupt_msi_mask_update(),
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.cfg_interrupt_msi_data(),
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.cfg_interrupt_msi_select('0),
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.cfg_interrupt_msi_int('0),
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.cfg_interrupt_msi_pending_status('0),
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.cfg_interrupt_msi_pending_status_data_enable('0),
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.cfg_interrupt_msi_pending_status_function_num('0),
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.cfg_interrupt_msi_sent(),
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.cfg_interrupt_msi_fail(),
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.cfg_interrupt_msi_attr('0),
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.cfg_interrupt_msi_tph_present('0),
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.cfg_interrupt_msi_tph_type('0),
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.cfg_interrupt_msi_tph_st_tag('0),
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.cfg_interrupt_msi_function_number('0),
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.sys_clk(clk_pcie),
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.sys_clk_gt(clk_pcie_gt),
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.sys_reset(pcie_reset_n),
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.phy_rdy_out(phy_rdy_out)
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);
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`endif
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endmodule |