Use 125MHz axi clock, 250 doesn't pass timing

artix_pcie.yaml

@@ -6,3 +6,11 @@ device_info:
 design_info:
   sources: "sources.list"
   top_module: "artix_pcie"
+
+synthesis_options:
+  synth_directive: "PerformanceOptimized"
+  opt_directive: "Explore"
+
+pnr_options:
+  place_directive: "Explore"
+  route_directive: "AggressiveExplore"

ip/xdma_0/xdma_0.xci

@@ -12,14 +12,14 @@
         "mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
         "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
-        "pl_link_cap_max_link_width": [ { "value": "X1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pl_link_cap_max_link_width": [ { "value": "X2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "pl_link_cap_max_link_speed": [ { "value": "2.5_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pl_link_cap_max_link_speed": [ { "value": "5.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],
         "axi_addr_width": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "axi_data_width": [ { "value": "64_bit", "resolve_type": "user", "usage": "all" } ],
-        "axisten_freq": [ { "value": "250", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "axisten_freq": [ { "value": "125", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "en_axi_slave_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "en_axi_master_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "pipe_sim": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -974,7 +974,7 @@
         "AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "CORE_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "USER_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USER_CLK_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "SILICON_REV": [ { "value": "Pre-Production", "resolve_type": "generated", "usage": "all" } ],
         "PIPE_SIM": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
         "VDM_EN": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],

requirements.txt

@@ -1,9 +1,8 @@
--i https://git.byronlathi.com/api/v4/projects/95/packages/pypi/simple
 scapy
 cocotb
 cocotbext-axi
 cocotbext-eth
 rtl-manifest
-build_fpga>=0.3.1
+build_fpga>=0.3.2
 fpga-sim>=0.1.0
 peakrdl

src/top.xdc

@@ -72,6 +72,7 @@ set_property PACKAGE_PIN C7  [get_ports {pci_exp_txn[0]}]
 
 set_property PACKAGE_PIN F10 [get_ports {pcie_exp_clkp}]
 set_property PACKAGE_PIN E10 [get_ports {pcie_exp_clkn}]
+create_clock -period 10.000 [get_ports pcie_exp_clkp]
 
 
 set_false_path -reset_path -from [get_clocks -of_objects [get_pins u_clk_wiz0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks rgmii_rxc]