bslathi19/artix_pcie
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ila for integrated pcie block

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This commit is contained in:
Byron Lathi
2025-02-26 22:28:40 -08:00
parent 1099b4ffdd
commit 1d15141420
6 changed files with 7118 additions and 1759 deletions
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135
src/artix_pcie.sv
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@@ -7,29 +7,33 @@ module artix_pcie(
input wire pcie_exp_clkp,
input wire pcie_exp_clkn,
output wire [0 : 0] pci_exp_txp,
output wire [0 : 0] pci_exp_txn,
input wire [0 : 0] pci_exp_rxp,
input wire [0 : 0] pci_exp_rxn,
output wire [1 : 0] pci_exp_txp,
output wire [1 : 0] pci_exp_txn,
input wire [1 : 0] pci_exp_rxp,
input wire [1 : 0] pci_exp_rxn,
output wire [3:0] led
);
logic pcie_refclk;
logic axi_aclk;
logic axi_aresetn;
logic axis_clk;
logic axis_rst;
logic link_up;
logic app_ready;
assign led[0] = ~link_up;
assign led[1] = ~app_ready;
logic [63:0] axis_tdata;
logic [7:0] axis_tkeep;
logic axis_tlast;
logic axis_tvalid;
logic axis_tready;
logic [21:0] axis_tuser;
logic [63 : 0] s_axis_c2h_tdata_0;
logic s_axis_c2h_tlast_0;
logic s_axis_c2h_tvalid_0;
logic s_axis_c2h_tready_0;
logic [7 : 0] s_axis_c2h_tkeep_0;
logic [63 : 0] m_axis_h2c_tdata_0;
logic m_axis_h2c_tlast_0;
logic m_axis_h2c_tvalid_0;
logic m_axis_h2c_tready_0;
logic [7 : 0] m_axis_h2c_tkeep_0;
IBUFDS_GTE2 #(
.CLKRCV_TRST("TRUE"),
@@ -43,46 +47,69 @@ IBUFDS_GTE2 #(
.ODIV2 ()
);
pcie_7x_0 u_pcie_7x_0 (
.pci_exp_txp (pci_exp_txp),
.pci_exp_txn (pci_exp_txn),
.pci_exp_rxp (pci_exp_rxp),
.pci_exp_rxn (pci_exp_rxn),
xdma_0 u_xdma (
.sys_clk(pcie_refclk),
.sys_rst_n(rst_n), // this reset is not synchronized. Should it be?
.user_lnk_up(led[0]),
.pci_exp_txp(pci_exp_txp[0]),
.pci_exp_txn(pci_exp_txn[0]),
.pci_exp_rxp(pci_exp_rxp[0]),
.pci_exp_rxn(pci_exp_rxn[0]),
.axi_aclk(axi_aclk),
.axi_aresetn(axi_aresetn),
.usr_irq_req('0),
.usr_irq_ack(),
.msi_enable(),
.msi_vector_width(),
.s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),
.s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),
.s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),
.s_axis_c2h_tready_0(s_axis_c2h_tready_0),
.s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0),
.m_axis_h2c_tdata_0(m_axis_h2c_tdata_0),
.m_axis_h2c_tlast_0(m_axis_h2c_tlast_0),
.m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0),
.m_axis_h2c_tready_0(m_axis_h2c_tready_0),
.m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0)
.user_clk_out (axis_clk),
.user_reset_out (axis_rst),
.user_lnk_up (link_up),
.user_app_rdy (app_ready),
.s_axis_tx_tready (),
.s_axis_tx_tdata ('0),
.s_axis_tx_tkeep ('0),
.s_axis_tx_tlast ('0),
.s_axis_tx_tvalid ('0),
.s_axis_tx_tuser ('0),
.m_axis_rx_tdata (axis_tdata),
.m_axis_rx_tkeep (axis_tkeep),
.m_axis_rx_tlast (axis_tlast),
.m_axis_rx_tvalid (axis_tvalid),
.m_axis_rx_tready (axis_tready),
.m_axis_rx_tuser (axis_tuser),
.cfg_interrupt ('0),
.cfg_interrupt_rdy (),
.cfg_interrupt_assert ('0),
.cfg_interrupt_di ('0),
.cfg_interrupt_do (),
.cfg_interrupt_mmenable (),
.cfg_interrupt_msienable(),
.cfg_interrupt_msixenable(),
.cfg_interrupt_msixfm (),
.cfg_interrupt_stat ('0),
.cfg_pciecap_interrupt_msgnum('0),
.sys_clk (pcie_refclk),
.sys_rst_n (rst_n),
.pcie_drp_clk ('0),
.pcie_drp_en ('0),
.pcie_drp_we ('0),
.pcie_drp_addr ('0),
.pcie_drp_di ('0),
.pcie_drp_do (),
.pcie_drp_rdy ()
);
axis_data_fifo_0 u_axis_data_fifo (
.s_axis_aresetn(axi_aresetn),
.s_axis_aclk(axi_aclk),
.s_axis_tvalid(m_axis_h2c_tvalid_0),
.s_axis_tready(m_axis_h2c_tready_0),
.s_axis_tdata(m_axis_h2c_tdata_0),
.s_axis_tkeep(m_axis_h2c_tkeep_0),
.s_axis_tlast(m_axis_h2c_tlast_0),
.m_axis_tvalid(s_axis_c2h_tvalid_0),
.m_axis_tready(s_axis_c2h_tready_0),
.m_axis_tdata(s_axis_c2h_tdata_0),
.m_axis_tkeep(s_axis_c2h_tkeep_0),
.m_axis_tlast(s_axis_c2h_tlast_0)
assign axis_tready = '1;
ila_0 u_ila_0 (
.clk (axis_clk),
.probe0 (axis_tready),
.probe1 (axis_tdata),
.probe2 (axis_tstrb),
.probe3 (axis_tvalid),
.probe4 (axis_tlast),
.probe5 (axis_tuser),
.probe6 (axis_tkeep),
.probe7 ('0),
.probe8 ('0)
);
endmodule
endmodule