Initial Commit

test/Makefile

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+.PHONY: clean
+
+clean:
+	rm -rf *.xml
+	rm -rf ip
+	rm -rf work*
+	rm -rf outflow

test/sources.list

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+src/sources.list

test/src/sources.list

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+test_top.sv
+test_module.sv

test/src/test_module.sv

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+module test_module (
+    input i_clk,
+    input i_rst,
+
+    output logic [31:0] o_count
+);
+
+logic [31:0] counter;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        counter <= '0;
+    end else begin
+        counter <= counter + 1;
+    end
+end
+
+assign o_count = counter;
+
+endmodule

test/src/test_top.sv

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+module test_top (
+    input i_clk,
+    input i_rst,
+
+    output o_led
+);
+
+logic [31:0] count;
+
+test_module u_test_module(
+    .i_clk      (i_clk),
+    .i_rst      (i_rst),
+
+    .o_count    (count)
+);
+
+assign o_led = count[31];
+
+endmodule

test/test.yaml

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+tool: "efinity"
+
+prj_info:
+  name: "test"
+  sw_version: "2024.2.294"
+
+device_info:
+  family: "Trion"
+  device: "T20F256"
+  timing_model: "I4"
+
+design_info:
+  unified_flow: True
+  verilog_version: "sv_09"
+  sources: "sources.list"
+  top_module: "test_top"
+
+
+constraint_info:
+  sdc_file: "constraints/constraints.sdc"
+
+isf_info: 
+  isf_file: "placement.isf"
+
+
+
+synthesis_options:
+  macros:
+    IFFT_PATH: "$REPO_TOP/src/sub/tx/sub/tx_dataplane/sub/ifft/fft-core/"
+
+pnr_options:
+  optimization_level: "TIMING_3"
+  placer_effort_level: 5
+
+pgm_options:
+
+debugger_options: