Initial Commit

test/src/sources.list

@@ -0,0 +1,2 @@
+test_top.sv
+test_module.sv

test/src/test_module.sv

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+module test_module (
+    input i_clk,
+    input i_rst,
+
+    output logic [31:0] o_count
+);
+
+logic [31:0] counter;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        counter <= '0;
+    end else begin
+        counter <= counter + 1;
+    end
+end
+
+assign o_count = counter;
+
+endmodule

test/src/test_top.sv

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+module test_top (
+    input i_clk,
+    input i_rst,
+
+    output o_led
+);
+
+logic [31:0] count;
+
+test_module u_test_module(
+    .i_clk      (i_clk),
+    .i_rst      (i_rst),
+
+    .o_count    (count)
+);
+
+assign o_led = count[31];
+
+endmodule